公开(公告)号：US20240099027A1

公开(公告)日：2024-03-21

申请号：US18179895

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Kensuke TAKAHASHI ,  Daisaburo TAKASHIMA ,  Naoki KAI ,  Yasumi ISHIMOTO

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10 ,  H10B63/34

Abstract: According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.