公开(公告)号：US20170364799A1

公开(公告)日：2017-12-21

申请号：US15182616

申请日：2016-06-15

申请人： Kneron Inc.

发明人： Chun-Chen Liu ,  Kangli Hao ,  Liu Liu

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06N3/082 ,  G06N3/04

摘要： An apparatus for deciding a simplification policy for a neural network is provided. The deciding apparatus has a plurality of artificial neurons, a receiving circuit, a memory, and a simplifying module. The plurality of artificial neurons are configured to form an original neural network. The receiving circuit receives a set of sample for training the original neural network. The memory is used for recording a plurality of learnable parameters for the original neural network. After the original neural network has been trained with the set of sample, the simplifying module abandons a part of neuron connections in the original neural network based on the learnable parameters recorded by the memory. The simplifying module accordingly decides the structure of a simplified neural network and a plurality of learnable parameters for the simplified neural network.

公开(公告)号：US20180053086A1

公开(公告)日：2018-02-22

申请号：US15243907

申请日：2016-08-22

申请人： Kneron Inc.

发明人： Chun-Chen Liu ,  Kangli Hao ,  Liu Liu

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/0481

摘要： A neural network including a controller and plural neurons is provided. The controller is configured to generate a forward propagation instruction in a computation process. Each neuron includes an instruction register, a storage device, and an application-specific computation circuit. The instruction register is configured to receive the forward propagation instruction from the controller and temporarily storing the forward propagation instruction. The storage device is configured to store at least one input and at least one learnable parameter. The application-specific computation circuit is invariably configured to dedicate to computations related to the neuron. In response to the forward propagation instruction received by the instruction register, the application-specific computation circuit is configured to perform a computation on the at least one input and the at least one learnable parameter according to an activation function and to feed back a computation result to the storage device.