公开(公告)号：US07564971B2

公开(公告)日：2009-07-21

申请号：US10800181

申请日：2004-03-12

申请人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

发明人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

IPC分类号： H04K1/00

CPC分类号： G06F7/728 ,  G06F7/5332

摘要： A signal processing apparatus for performing modular multiplication for use in a signal processing system includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock. The present invention provides a high-speed modular multiplication apparatus with fewer gates and reduced power consumption.

摘要翻译： 用于在信号处理系统中使用的用于执行模乘的信号处理装置包括：第一逻辑，用于通过根据乘法器的乘法器的Booth转换结果选择性地对被乘数执行补码操作来输出有符号被乘数; 基于从用于校正前一时钟的进位值cin确定的当前时钟的进位输入值进位以及被乘数的符号位，输出在乘法中被签名的模数的第二逻辑; 以及用于接收经签名被乘数和符号模数的第三逻辑，以及通过对在前一个发现的完整加法运算的进位值C和总和值S迭代地执行全加法运算来计算乘法运算的结果值 时钟。 本发明提供一种具有较少闸门和降低的功耗的高速乘法装置。

公开(公告)号：US08209369B2

公开(公告)日：2012-06-26

申请号：US11849880

申请日：2007-09-04

申请人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

发明人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F15/00 ,  G06F7/52

CPC分类号： G06F7/728 ,  G06F7/5332

摘要： Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic device, includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock.

摘要翻译： 提供了一种用于移动通信环境中的加密/解密和电子签名的装置。 一种信号处理装置，在电子设备中执行模乘，包括：第一逻辑，用于通过根据乘法器的乘法器的B乘转换结果选择性地对被乘数执行补码运算来输出有符号被乘数; 基于从用于校正前一时钟的进位值cin确定的当前时钟的进位输入值进位以及被乘数的符号位，输出在乘法中被签名的模数的第二逻辑; 以及用于接收经签名被乘数和符号模数的第三逻辑，以及通过对在前一个发现的完整加法运算的进位值C和总和值S迭代地执行全加法运算来计算乘法运算的结果值 时钟。

公开(公告)号：US20080065713A1

公开(公告)日：2008-03-13

申请号：US11849880

申请日：2007-09-04

申请人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

发明人： Kyung-Hee Lee ,  Bum-Jin Im ,  Mi-Suk Huh

IPC分类号： G06F7/38

CPC分类号： G06F7/728 ,  G06F7/5332

摘要： Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic device, includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock.

摘要翻译： 提供了一种用于移动通信环境中的加密/解密和电子签名的装置。 一种信号处理装置，在电子设备中执行模乘，包括：第一逻辑，用于通过根据乘法器的乘法器的B乘转换结果选择性地对被乘数执行补码运算来输出有符号被乘数; 基于从用于校正前一时钟的进位值cin确定的当前时钟的进位输入值进位以及被乘数的符号位，输出在乘法中被签名的模数的第二逻辑; 以及用于接收经签名被乘数和符号模数的第三逻辑，以及通过对在前一个发现的完整加法运算的进位值C和总和值S迭代地执行全加法运算来计算乘法运算的结果值 时钟。