公开(公告)号：US09111807B2

公开(公告)日：2015-08-18

申请号：US14084283

申请日：2013-11-19

Applicant: LG DISPLAY CO., LTD.

Inventor： Hun Jang ,  Joon Young Yang ,  Gyu Tae Kang

IPC: H01L27/12 ,  H01L27/16

CPC classification number: H01L27/124 ,  H01L27/1222

Abstract: A thin film transistor substrate includes: pluralities of gate lines and data lines arranged to define a plurality of pixel regions, and a plurality of thin film transistors formed on the pixel regions in such a manner as to include first and second thin film transistors connected to the same gate line and the pixel regions adjacent to each other. Each of the first and second thin film transistors includes: a gate electrode connected to the gate line; a semiconductor layer formed on the gate line in an octagon shape; a source electrode connected to the data line; and a drain electrode formed in an opposite shape to the source electrode.

Abstract translation: 薄膜晶体管基板包括：多个栅极线和数据线，被布置为限定多个像素区域，以及形成在像素区域上的多个薄膜晶体管，其包括第一和第二薄膜晶体管，其连接到 相同的栅极线和彼此相邻的像素区域。 第一和第二薄膜晶体管中的每一个包括：连接到栅极线的栅电极; 形成在八边形形状的栅极线上的半导体层; 连接到数据线的源电极; 以及与源极形成为相反形状的漏电极。

公开(公告)号：US20140138691A1

公开(公告)日：2014-05-22

申请号：US14084283

申请日：2013-11-19

Applicant: LG DISPLAY CO., LTD.

Inventor： Hun Jang ,  Joon Young Yang ,  Gyu Tae Kang

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1222

Abstract: A thin film transistor substrate includes: pluralities of gate lines and data lines arranged to define a plurality of pixel regions, and a plurality of thin film transistors formed on the pixel regions in such a manner as to include first and second thin film transistors connected to the same gate line and the pixel regions adjacent to each other. Each of the first and second thin film transistors includes: a gate electrode connected to the gate line; a semiconductor layer formed on the gate line in an octagon shape; a source electrode connected to the data line; and a drain electrode formed in an opposite shape to the source electrode.

Abstract translation: 薄膜晶体管基板包括：多个栅极线和数据线，被布置为限定多个像素区域，以及形成在像素区域上的多个薄膜晶体管，其包括第一和第二薄膜晶体管，其连接到 相同的栅极线和彼此相邻的像素区域。 第一和第二薄膜晶体管中的每一个包括：连接到栅极线的栅电极; 形成在八边形形状的栅极线上的半导体层; 连接到数据线的源电极; 以及与源电极形成为相反形状的漏电极。