Abstract:
A light emitting display apparatus is disclosed. The light emitting display apparatus includes: a substrate; and a plurality of pixels disposed on a pixel area on the substrate. Each of the plurality of pixels includes: a first circuit layer including a first pixel circuit including a driving transistor; a second circuit layer overlapping the first circuit layer, wherein the second circuit layer includes a second pixel circuit including a data supply transistor configured to supply a data signal to the first pixel circuit; a circuit insulating layer between the first circuit layer and the second circuit layer; and a light emitting diode layer including a light emitting diode electrically connected with the first pixel circuit.
Abstract:
The present specification relates to a display device in which an ultra-high resolution can be implemented at half the prices of conventional display devices. To achieve the same, in the display device of the present specification, small-sized and ultra-high resolution pixels may be disposed in a central area of a display panel, and pixels greater and cheaper than the pixels disposed in the central area may be disposed in a peripheral active area surrounding the central area.
Abstract:
Discussed is an electroluminescence display that can include a substrate; and a plurality of pixels on the substrate. Each pixel can include a first electrode, a light emission layer on the first electrode, and a second electrode on the light emission layer. Each pixel can also include a half transparent layer on the second electrode, and a color filter on the half transparent layer.
Abstract:
Disclosed is a display device including: a display panel; a timing controller generating image data corresponding to an input image, and generating and outputting a first start signal, an on clock, and an off clock; a level shifter generating a second start signal in synchronization with the first start signal, generating gate clocks that swing to a predetermined voltage and have multiple phases, by using the on clock and the off clock, and outputting the generated gate clocks; a shift register including multiple stages connected to gate lines of the display panel, respectively, and outputting a scan signal sequentially to the gate lines by using the second start signal and the gate clocks; and a data driving circuit supplying a data voltage corresponding to the image data to data lines of the display panel in synchronization with the scan signal.
Abstract:
A display device includes a source unit; and a sink unit connected with the source unit via an embedded display port interface for signal transmission between the source and sink units and to enable a panel self refresh (PSR) mode for reducing power, wherein, for an input still image, the source unit applies power to a frame buffer of the sink unit and transmits the still image to the sink unit, wherein the sink unit determines whether the still image can be losslessly compressed and stored in the frame buffer, outputs a first control signal if the still image can be losslessly compressed and stored in the frame buffer, and outputs a second control signal if the still image cannot be losslessly compressed and stored, and wherein the source unit activates the PSR mode for the first control signal, and deactivates the PSR mode for the second control signal.
Abstract:
A display device A display device includes a display panel including a plurality of pixel rows and a plurality of pixel columns arranged to display an image; a data driver comprising a plurality of source drive integrated circuits (ICs) respectively connected to one or more pixel columns among the plurality of pixel columns and configured to supply a data signal to the plurality of pixel rows; and a timing controller configured to supply image data and a data control signal to the data driver, wherein the timing controller includes a general purpose input-output (GPIO) pin connected to digital block power down enable (DBDEN) pins provided in each of the plurality of source drive ICs in a point-to-multipoint way and outputs a DBDEN signal disabling to at least some of the plurality of source drive ICs.