公开(公告)号：US12058909B2

公开(公告)日：2024-08-06

申请号：US17517394

申请日：2021-11-02

Applicant: LG DISPLAY CO., LTD.

Inventor： Jae-Woong Youn ,  Kiwon Son ,  Minseon Park

IPC: H10K59/131 ,  G09G3/3225 ,  H10K59/122

CPC classification number: H10K59/1315 ,  G09G3/3225 ,  H10K59/122 ,  G09G2310/0264

Abstract: Embodiments of the present disclosure are related to a display device, as disposing a clock signal line on an area overlapping with an area where a gate circuit is disposed on a non-active area of a display panel, a gate driving circuit can be disposed on the non-active area while minimizing an increase of the non-active area. Furthermore, as disposing the clock signal line by using metal layers that a first metal layer with a low resistance and a second metal layer with a high reflectance are stacked, the clock signal line disposed on the non-active area and a pixel electrode disposed on an active area can be implemented as a same layer, the clock signal line disposed on the gate circuit can be implemented while reducing the number of masks.