专利检索 ap:("LG Display Co., Ltd.") AND inv:"Hangyu Jung" 第 1 页

1.

发明授权
Display device and method of manufacturing same 有权

公开(公告)号：US11985871B2

公开(公告)日：2024-05-14

申请号：US17128929

申请日：2020-12-21

申请人： LG Display Co., Ltd.

发明人： Yongsun Jo , Woojung Byun , Hangyu Jung , Deuksoo Jung

IPC分类号： H10K59/131 , H10K59/122 , H10K59/12

CPC分类号： H10K59/131 , H10K59/122 , H10K59/1201

摘要： Provided are a display device and a method of manufacturing the display device, the display device including a substrate including a pixel area where a pixel is placed, and a wire area where wires connected to the pixel are placed, a first power line placed on the substrate, and through which driving power is applied to the pixel, an active layer including a first connection pattern, a second connection pattern, and a third connection pattern that are placed above the first power line in the wire area, the third connection pattern being connected to the first power line, and a first gate line connected to the first connection pattern, and a second gate line connected to the second connection pattern, the first gate line and the second gate line being placed on the active layer in the wire area, wherein the first to the third connection pattern are island-shaped electrodes.

2.

发明授权
Display panel and manufacturing method thereof 有权

公开(公告)号：US12108648B2

公开(公告)日：2024-10-01

申请号：US17546674

申请日：2021-12-09

申请人： LG Display Co., Ltd.

发明人： Hangyu Jung , Woojung Byun

IPC分类号： H10K59/35 , G09G3/3233 , H01L27/12 , H10K59/12 , H10K59/121

CPC分类号： H10K59/353 , G09G3/3233 , H10K59/1213 , H10K59/1216 , H10K59/1201

摘要： A display panel having an improved opening ratio and a manufacturing method of the display panel are discussed. In the display panel, a storage capacitor includes a bottom electrode, a buffer layer disposed on the bottom electrode, a middle electrode covering a portion of the buffer layer, a gate insulating layer covering the middle electrode and the buffer layer, and an upper electrode covering a portion of the gate insulating layer. In the buffer layer, a thickness of a first area covering the middle electrode is greater than a thickness of a second area that is in contact with the gate insulating layer.