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公开(公告)号：US11263988B2
公开(公告)日：2022-03-01
申请号：US15723958
申请日：2017-10-03
Applicant: LG Display Co., Ltd.
Inventor： Yeonkyung Kim , Taewoong Moon , Junghyun Lee
IPC: G11C19/00 , G09G3/36 , G09G3/3266 , G06F3/041 , G11C19/28
Abstract: The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.
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公开(公告)号：US10534477B2
公开(公告)日：2020-01-14
申请号：US15798011
申请日：2017-10-30
Applicant: LG DISPLAY CO., LTD.
Inventor： Yeonkyung Kim , Taewoong Moon , Junghyun Lee
Abstract: A gate driver and a display device having an in-cell touch sensor using the gate driver are disclosed. The gate driver includes a shift register configured to sequentially supply gate pulses to gate lines of a display panel. The shift register includes an (N−1)th stage, where N is a positive integer equal to or greater than 2, configured to output an (N−1)th gate pulse, an Nth stage configured to output an Nth gate pulse, and a hold circuit configured to hold an output voltage of the (N−1)th stage during a predetermined time and supply the output voltage to the Nth stage.
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公开(公告)号：US10573225B2
公开(公告)日：2020-02-25
申请号：US15720869
申请日：2017-09-29
Applicant: LG DISPLAY CO., LTD.
Inventor： Junghyun Lee , Taewoong Moon , Yeonkyung Kim
Abstract: A gate drive circuit and a display device are provided. The gate drive circuit comprises: a first stage that outputs a first gate pulse at a first output terminal by increasing a voltage at the first output terminal when a first Q node is charged in response to receiving a first carry signal at a first start terminal, and decreasing the voltage at the first output terminal when a first QB node is charged; and a second stage that outputs a second gate pulse at a second output terminal and outputs a second carry signal at a third output terminal by increasing voltages at the second and third output terminals when a second Q node is charged in response to receiving the first carry signal at a second start terminal, and decreasing the voltages at the second and third output terminals when a second QB node is charged.
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