公开(公告)号：US09306552B1

公开(公告)日：2016-04-05

申请号：US14593813

申请日：2015-01-09

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Ciaran J. Brennan ,  Mukesh Kumar

IPC: H03K17/00 ,  H03K5/1532

CPC classification number: H03K5/1532 ,  H01L27/0883

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

Abstract translation: 最大电压选择电路可以包括多个输入，每个用于接收不同的输入电压，用于输送最高输入电压的输出，以及电压选择电路。 电压选择电路可以自动选择具有最大电压幅值的输入端，将所选输入端的电压自动输出到输出端，并且不从任何输入端抽取静态工作电流。 对于多个输入中的两个的每个独特组合，电压选择电路可以包括增强型FET，其中通道串联连接在两个输入的唯一组合的第一输入和输出之间; 增强型FET的栅极与通过耗尽型FET的沟道的两个输入的独特组合的第二输入端之间的连接; 一个附加的增强型FET，其中通道串联在第二个两个输入和输出的唯一组合之间; 以及附加增强型FET的栅极和通过附加耗尽型FET的沟道的两个输入的唯一组合中的第一个之间的连接。

公开(公告)号：US09685938B2

公开(公告)日：2017-06-20

申请号：US15019394

申请日：2016-02-09

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Ciaran J. Brennan ,  Mukesh Kumar

IPC: H03K17/00 ,  H03K5/1532 ,  H01L27/088

CPC classification number: H03K5/1532 ,  H01L27/0883

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

公开(公告)号：US20160156341A1

公开(公告)日：2016-06-02

申请号：US15019394

申请日：2016-02-09

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Ciaran J. Brennan ,  Mukesh Kumar

IPC: H03K5/1532 ,  H01L27/088

CPC classification number: H03K5/1532 ,  H01L27/0883

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

Abstract translation: 最大电压选择电路可以包括多个输入，每个用于接收不同的输入电压，用于输送最高输入电压的输出，以及电压选择电路。 电压选择电路可以自动选择具有最大电压幅值的输入端，将所选输入端的电压自动输出到输出端，并且不从任何输入端抽取静态工作电流。 对于多个输入中的两个的每个独特组合，电压选择电路可以包括增强型FET，其中通道串联连接在两个输入的唯一组合的第一输入和输出之间; 增强型FET的栅极与通过耗尽型FET的沟道的两个输入的独特组合的第二输入端之间的连接; 一个附加的增强型FET，其中通道串联在第二个两个输入和输出的唯一组合之间; 以及附加增强型FET的栅极和通过附加耗尽型FET的沟道的两个输入的唯一组合中的第一个之间的连接。