公开(公告)号：US10693373B2

公开(公告)日：2020-06-23

申请号：US16112593

申请日：2018-08-24

Applicant: LINEAR TECHNOLOGY HOLDING LLC

Inventor： Jian Li ,  San-Hwa Chee

IPC: H02M1/08 ,  H02M3/158 ,  H02M1/00

Abstract: A hybrid power converter includes a switching circuit, an LC circuit, and a detection circuit. The switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at an output port across one of the switching transistors. The LC circuit may be coupled to the output port of the switching circuit to receive the series of pulses and to generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The detection circuit may be coupled to the switching circuit and may generate a low frequency portion of the inductor current based on one or more currents of the switching transistors to adjust the switching cycle based at least on the low frequency portion.

公开(公告)号：US10389237B1

公开(公告)日：2019-08-20

申请号：US15957845

申请日：2018-04-19

Applicant: Linear Technology Holding LLC

Inventor： San-Hwa Chee ,  Yingyi Yan

IPC: H02M3/07 ,  H02M3/158 ,  H02M1/00

Abstract: The subject disclosure includes reducing switching losses at lower load current while maintaining the switching frequency for a hybrid switched capacitor converter circuit. Control circuitry is coupled to the hybrid switched capacitor converter circuit and configured to measure a load current at an output of the hybrid switched capacitor converter circuit in a buck phase mode. The control circuitry is configured to compare the measured load current to set of predetermined thresholds. The control circuitry is configured to drive a first voltage to the second set of transistors that turns on the second set of transistors periodically to regulate the output during the buck phase mode. The control circuitry is also configured to drive a second voltage to the first set of transistors that turns off the first set of transistors for one or more switching cycles while the second set of transistors are turned on based on the comparison.