公开(公告)号：US20230058571A1

公开(公告)日：2023-02-23

申请号：US17820850

申请日：2022-08-18

Applicant: LX Semicon Co., Ltd.

Inventor： Jin Su BYEON ,  Cheol Ho LEE

IPC: G09G3/20

Abstract: A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

公开(公告)号：US20230043062A1

公开(公告)日：2023-02-09

申请号：US17863313

申请日：2022-07-12

Applicant: LX Semicon Co., Ltd.

Inventor： Jin Su BYEON ,  Cheol Ho LEE ,  Yoon Soo SHIN

IPC: G09G3/20

Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

公开(公告)号：US20230018128A1

公开(公告)日：2023-01-19

申请号：US17862302

申请日：2022-07-11

Applicant: LX Semicon Co., Ltd.

Inventor： Jin Su BYEON ,  Cheol Ho LEE ,  Yoon Soo SHIN

IPC: G09G3/20

Abstract: The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.