公开(公告)号：US07009427B1

公开(公告)日：2006-03-07

申请号：US10142740

申请日：2002-05-08

申请人： Lei Wang ,  Qiang Li ,  Jianbin Wu

发明人： Lei Wang ,  Qiang Li ,  Jianbin Wu

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A low power dynamic circuit with an inverter-like output is disclosed. The dynamic circuit includes a precharge circuit, a discharge circuit, and an output circuit. The precharge circuit charges a precharge node from the clock signal when the data input signal is low and the clock input is high. The discharge circuit discharges a discharge node to the clock signal when the data input signal is high and the clock input is low. The output circuit is an inverter-like configuration that uses the precharge node to generate a logic high and the discharge node to generate a logic low, as required by the data input signal. In one embodiment, the precharge circuit is operative with a first clock and the discharge circuit is operative with a second clock. In yet another embodiment, there is only a precharge circuit and an output circuit.

摘要翻译： 公开了一种具有逆变器输出的低功率动态电路。 动态电路包括预充电电路，放电电路和输出电路。 当数据输入信号为低电平且时钟输入为高电平时，预充电电路从时钟信号对预充电节点充电。 当数据输入信号为高电平且时钟输入为低电平时，放电电路将放电节点放电至时钟信号。 输出电路是类似逆变器的配置，其使用预充电节点来产生逻辑高电平，并且放电节点根据数据输入信号的要求产生逻辑低电平。 在一个实施例中，预充电电路与第一时钟一起工作，并且放电电路与第二时钟一起工作。 在另一个实施例中，仅存在预充电电路和输出电路。

公开(公告)号：US06784696B1

公开(公告)日：2004-08-31

申请号：US10371238

申请日：2003-02-19

申请人： Lei Wang ,  Qiang Li ,  Jianbin Wu

发明人： Lei Wang ,  Qiang Li ,  Jianbin Wu

IPC分类号： H03K19096

CPC分类号： H03K19/0019

摘要： Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

公开(公告)号：US20060055429A1

公开(公告)日：2006-03-16

申请号：US11269776

申请日：2005-11-07

申请人： Lei Wang ,  Qiang Li ,  Jianbin Wu

发明人： Lei Wang ,  Qiang Li ,  Jianbin Wu

IPC分类号： H03K19/096

CPC分类号： H03K19/0019

摘要： Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the loic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

摘要翻译： 公开了使用再生能源的动态低功率逻辑。 逻辑电路具有放电路径，预充电路径和控制电路。 预充电路径是耦合在时钟线和电路的输出节点之间的PMOS晶体管，并配置为在预充电阶段期间将输出节点充电到时钟线的高电压。 在评估阶段期间，放电路径计算输出节点所需的逻辑功能。 控制电路连接在输出节点与时钟线之间，连接到预充电路径晶体管的栅极。 控制电路提供适当的栅极驱动，无论输出节点上的电压或放电路径的输入如何，以确保预充电晶体管将输出节点完全充电到时钟线的逻辑高电压，从而提供循环能量 用于操作电路。

公开(公告)号：US06552574B1

公开(公告)日：2003-04-22

申请号：US10087604

申请日：2002-03-01

申请人： Lei Wang ,  Qiang Li ,  Jianbin Wu

发明人： Lei Wang ,  Qiang Li ,  Jianbin Wu

IPC分类号： H03K19096

CPC分类号： H03K19/0019

摘要： Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

摘要翻译： 公开了使用再生能源的动态低功率逻辑。 逻辑电路具有放电路径，预充电路径和控制电路。 预充电路径是耦合在时钟线和电路的输出节点之间的PMOS晶体管，并配置为在预充电阶段期间将输出节点充电到时钟线的逻辑高电压。 在评估阶段期间，放电路径计算输出节点所需的逻辑功能。 控制电路连接在输出节点与时钟线之间，连接到预充电路径晶体管的栅极。 控制电路提供适当的栅极驱动，无论输出节点上的电压或放电路径的输入如何，以确保预充电晶体管将输出节点完全充电到时钟线的逻辑高电压，从而提供循环能量 用于操作电路。

公开(公告)号：US06909319B2

公开(公告)日：2005-06-21

申请号：US10900954

申请日：2004-07-27

申请人： Lei Wang ,  Jianbin Wu

发明人： Lei Wang ,  Jianbin Wu

IPC分类号： H02M3/07 ,  H03K17/06 ,  G05F1/10

CPC分类号： H02M3/073 ,  H03K17/063

摘要： A low power charge pump system having a plurality of charge pump cells. Each cell is a three transistor device that operates to transfer voltage from an input node to an output node of the cell when the input voltage is substantially greater than the output voltage and to block when the output voltage is substantially greater than the input voltage. Each cell has a pump capacitor is connected between a clock and its output, the odd-numbered cells having a first clock connected to their pump capacitors and the even-numbered cells having a second clock connected to their pump capacitors. During a first phase of either the first or second clock, the cell operates to transfer a voltage on its input node to its output node and during a second phase, the cell operates to boost its output voltage by a predetermined amount.

摘要翻译： 一种具有多个电荷泵电池的低功率电荷泵系统。 当输入电压基本上大于输出电压并且当输出电压基本上大于输入电压时，每个单元是工作以将电压从输入节点传送到单元的输出节点的三晶体管器件。 每个单元具有连接在时钟与其输出之间的泵电容器，奇数单元具有连接到其泵浦电容器的第一时钟，并且偶数单元具有连接到其泵电容器的第二时钟。 在第一或第二时钟的第一阶段期间，单元操作以将其输入节点上的电压传送到其输出节点，并且在第二阶段期间，单元操作以将其输出电压升高预定量。

公开(公告)号：US07176746B1

公开(公告)日：2007-02-13

申请号：US10294042

申请日：2002-11-12

申请人： Lei Wang ,  Jianbin Wu

发明人： Lei Wang ,  Jianbin Wu

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H03K17/063

摘要： A low power charge pump system having a plurality of charge pump cells. Each cell is a three transistor device that operates to transfer voltage from an input node to an output node of the cell when the input voltage is substantially greater than the output voltage and to block when the output voltage is substantially greater than the input voltage. Each cell has a pump capacitor is connected between a clock and its output, the odd-numbered cells having a first clock connected to their pump capacitors and the even-numbered cells having a second clock connected to their pump capacitors. During a first phase of either the first or second clock, the cell operates to transfer a voltage on its input node to its output node and during a second phase, the cell operates to boost its output voltage by a predetermined amount.

摘要翻译： 一种具有多个电荷泵电池的低功率电荷泵系统。 当输入电压基本上大于输出电压并且当输出电压基本上大于输入电压时，每个单元是工作以将电压从输入节点传送到单元的输出节点的三晶体管器件。 每个单元具有连接在时钟与其输出之间的泵电容器，奇数单元具有连接到其泵浦电容器的第一时钟，并且偶数单元具有连接到其泵电容器的第二时钟。 在第一或第二时钟的第一阶段期间，单元操作以将其输入节点上的电压传送到其输出节点，并且在第二阶段期间，单元操作以将其输出电压升高预定量。

公开(公告)号：US06812745B1

公开(公告)日：2004-11-02

申请号：US10388841

申请日：2003-03-14

申请人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

发明人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

IPC分类号： H03K19096

CPC分类号： H02M3/073 ,  H03K17/063 ,  H03K19/0963

摘要： A method and aparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. The energy storage circuitry oscillates with a determinable period and is tunable so that its oscillations can be synchronized to a clock.

摘要翻译： 一种用循环能量操作逻辑电路的方法和装置。 使用具有用于存储能量的节点和连接到能量存储电路的返回节点的逻辑电路。 逻辑电路使用存储在节点上的能量来操作，以在第一阶段期间基于逻辑输入来确定逻辑输出。 能量存储电路在逻辑电路的操作期间捕获存储的能量的一部分，并且在第二阶段期间将所捕获的能量的一部分传送回节点。 能量存储电路以可确定的周期振荡，并且是可调谐的，使得其振荡可以与时钟同步。

公开(公告)号：US20050077922A1

公开(公告)日：2005-04-14

申请号：US10922182

申请日：2004-08-18

申请人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

发明人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

IPC分类号： H02M3/07 ,  H03K17/06 ,  H03K19/096

CPC分类号： H02M3/073 ,  H03K17/063 ,  H03K19/0963

摘要： A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. The energy storage circuitry oscillates with a determinable period and is tunable so that its oscillations can be synchronized to a clock.

摘要翻译： 一种用循环能量操作逻辑电路的方法和装置。 使用具有用于存储能量的节点和连接到能量存储电路的返回节点的逻辑电路。 逻辑电路使用存储在节点上的能量来操作，以在第一阶段期间基于逻辑输入来确定逻辑输出。 能量存储电路在逻辑电路的操作期间捕获存储的能量的一部分，并且在第二阶段期间将所捕获的能量的一部分传送回节点。 能量存储电路以可确定的周期振荡，并且是可调谐的，使得其振荡可以与时钟同步。

公开(公告)号：US06559681B1

公开(公告)日：2003-05-06

申请号：US09967189

申请日：2001-09-27

申请人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

发明人： Jianbin Wu ,  Weiwei Guo ,  Yuan Yao

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K17/063

摘要： A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. In one embodiment, the logic circuitry and the energy storage circuitry form a resonant circuit and the logic circuitry operates synchronously to a clock. In another embodiment, the energy storage circuitry includes a resonant circuit configured to oscillate with a determinable period. The resonant circuit is tunable so that its oscillations can be synchronized to a clock.

摘要翻译： 一种用循环能量操作逻辑电路的方法和装置。 使用具有用于存储能量的节点和连接到能量存储电路的返回节点的逻辑电路。 逻辑电路使用存储在节点上的能量来操作，以在第一阶段期间基于逻辑输入来确定逻辑输出。 能量存储电路在逻辑电路的操作期间捕获存储的能量的一部分，并且在第二阶段期间将所捕获的能量的一部分传送回节点。 在一个实施例中，逻辑电路和能量存储电路形成谐振电路，逻辑电路与时钟同步工作。 在另一个实施例中，能量存储电路包括配置成以可确定的周期振荡的谐振电路。 谐振电路是可调谐的，使得其振荡可以与时钟同步。

公开(公告)号：US06448816B1

公开(公告)日：2002-09-10

申请号：US09614494

申请日：2000-07-11

申请人： Jianbin Wu

发明人： Jianbin Wu

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K17/063

摘要： A method and apparatus for operating logic circuitry with recycled energy. An energy storage device such as an inductor collects energy that used to operate logic circuitry during a first phase of a clock cycle and returns the collected energy back to the circuit during a second phase of the clock cycle. An adaptive circuit senses the collected energy that is returned to the logic circuit during the second phase of the clock cycle to determine whether the energy has fallen below a predetermined limit. If so, the adaptive circuit supplies any needed energy during the second phase of the clock cycle. The inductor that collects energy used to operate the logic circuitry and the inherent capacitance of the logic circuitry form a resonant circuit that operates in synchronism with the clock cycle, the inductor storing energy during the first phase and returning the energy to the inherent capacitance of the logic circuitry during the second phase. For complex logic functions, a plurality of blocks of logic circuitry are joined together in a pipeline, so that after a given number of clocks the complex logic function is computed. Pipelining also permits the energy restoring time of each block during the second phase of the clock cycle to be overlapped with the logic computing time at each block during the first phase of the clock, so that no extra clock cycles are required for restoring the energy of each block.

摘要翻译： 一种用循环能量操作逻辑电路的方法和装置。 诸如电感器的能量存储装置收集用于在时钟周期的第一阶段期间操作逻辑电路的能量，并且在时钟周期的第二阶段期间将收集的能量返回到电路。 自适应电路感测在时钟周期的第二阶段期间返回到逻辑电路的收集的能量，以确定能量是否已经下降到预定极限以下。 如果是这样，自适应电路在时钟周期的第二阶段提供所需的能量。 收集用于操作逻辑电路的能量和逻辑电路的固有电容的电感器形成与时钟周期同步操作的谐振电路，电感器在第一阶段期间存储能量并将能量返回到 逻辑电路在第二阶段。 对于复杂的逻辑功能，多个逻辑电路块在流水线中连接在一起，使得在给定数量的时钟之后，计算复杂逻辑功能。 流水线还允许在时钟周期的第二阶段期间每个块的能量恢复时间与在时钟的第一阶段期间的每个块处的逻辑计算时间重叠，使得不需要额外的时钟周期来恢复 每个块。