NAND-type Flash Array with Reduced Inter-cell Coupling Resistance
    1.
    发明申请
    NAND-type Flash Array with Reduced Inter-cell Coupling Resistance 审中-公开
    具有减小的小区间耦合电阻的NAND型闪存阵列

    公开(公告)号:US20090085069A1

    公开(公告)日:2009-04-02

    申请号:US11862841

    申请日:2007-09-27

    申请人: Len MEI Yue-Song HE

    发明人: Len MEI Yue-Song HE

    IPC分类号: H01L27/10 H01L21/82

    摘要: In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel.

    摘要翻译: 在NAND型非易失性可再编程存储器阵列中,相邻存储单元之间的单元间耦合电阻通过形成嵌入在单元间耦合区域的扩散区中的金属硅化物嵌入来减少。 扩散区包括浅植入区和深植入区。 在一个实施例中,浅注入区域限定用于存储器单元的浮栅晶体管的浅源/漏区。 控制金属硅化物插入的尺寸以不损害由浅和深植入区域限定的隔离PN结。 在一个实施例中,金属硅化物插入物包括镍。