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1.发明授权公开(公告)号：US07684563B1
公开(公告)日：2010-03-23
申请号：US10968428
申请日：2004-10-19
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm is dynamically selectable from a plurality of hash algorithms, and where the hash logic comprises a plurality of pipeline stages each configured to compute a portion of the hash algorithm. The cryptographic unit may further include a word buffer configured to store the data block during computing by the hash logic.
摘要翻译： 一种用于实现统一哈希算法流水线的装置和方法。 在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法计算数据块的哈希值，其中散列算法可以从多个散列算法动态地选择，并且其中散列逻辑包括多个 流水线级分别被配置为计算散列算法的一部分。 加密单元还可以包括字缓冲器，其被配置为在由哈希逻辑计算期间存储数据块。
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公开(公告)号：US07443981B1
公开(公告)日：2008-10-28
申请号：US10676554
申请日：2003-10-01
IPC分类号： H04K1/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 适于执行数据加密标准的至少一部分的执行单元。 执行单元包括左半输入; 一键输入 和一个表输入。 执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。 执行单元还包括具有两个输入和一个输出的第一个异或运算符。 第一个独占或运算符被配置为接收左半输入和键输入。 执行单元还包括具有两个输入和一个输出的第二个异或运算符。 第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。 执行单元还包括具有两个输入和一个输出的第三个异或运算符。 第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。
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公开(公告)号：US20120087492A1
公开(公告)日：2012-04-12
申请号：US13291026
申请日：2011-11-07
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 描述了用于执行包括左半输入的数据加密标准的至少一部分的执行单元; 一键输入 和Table输入，以及被配置为接收Table输入的第一组晶体管，执行表查找和输出数据。 执行单元还包括具有两个输入的第一异或运算符和被配置为接收左半输入和键输入的输出。 执行单元还包括具有两个输入的第二异或运算符和被配置为接收由第一组晶体管输出的数据并且接收第一个异或运算符的输出的输出。 执行单元还包括具有两个输入的第三异或运算符和被配置为接收左半输入和由第一组晶体管输出的数据的输出。
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4.发明申请INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS 审中-公开使用通用寄存器执行数据加密标准（DES）计算的说明公开(公告)号：US20100329450A1
公开(公告)日：2010-12-30
申请号：US12494481
申请日：2009-06-30
IPC分类号： H04L9/06
CPC分类号： H04L9/0625 , H04L2209/122 , H04L2209/125
摘要： Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor.
摘要翻译： 本发明的一些实施例提供一种处理器，其包括一组通用寄存器和至少一个执行单元。 通用寄存器组中的每个通用寄存器至少为64位宽，执行单元支持一个或多个数据加密标准（DES）指令。 具体地，执行单元可以支持用于执行DES置换操作和DES旋转操作的置换旋转指令。 执行单元还可以支持执行DES循环操作的循环指令。 由于DES指令使用通用寄存器而不是专用寄存器来执行DES特定操作，所以处理器的电路复杂度和面积减少。 此外，在一些实施例中，由于DES指令需要至多两个操作数，所以指定操作数的位置所需的位数减少，从而使更多数量的指令由处理器支持。
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公开(公告)号：US07720219B1
公开(公告)日：2010-05-18
申请号：US10968406
申请日：2004-10-19
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a hash algorithm word buffer. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm includes a plurality of iterations, and where the data block includes a plurality of data words. The cryptographic unit may further include a word buffer comprising a plurality of data word positions and configured to store the data block during computing by the hash logic, where subsequent to the hash logic computing one of the iterations of the hash algorithm, the word buffer is further configured to linearly shift the data block by one or more data word positions according to the hash algorithm. The hash algorithm may be dynamically selectable from a plurality of hash algorithms.
摘要翻译： 一种用于实现散列算法字缓冲器的装置和方法。 在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法来计算数据块的哈希值，其中散列算法包括多个迭代，并且其中数据块包括多个数据字。 加密单元还可以包括字缓冲器，该字缓冲器包括多个数据字位置，并且被配置为在散列逻辑的计算期间存储该数据块，其中在散列逻辑之后计算散列算法的迭代之一，字缓冲器 还被配置为根据所述散列算法将所述数据块线性移位一个或多个数据字位置。 散列算法可以从多个散列算法中动态地选择。
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公开(公告)号：US07711955B1
公开(公告)日：2010-05-04
申请号：US10939530
申请日：2004-09-13
CPC分类号： H04L9/0637 , G06F9/3851 , H04L9/0894 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for cryptographic key expansion. According to a first embodiment, a cryptographic unit may include key storage configured to store an expanded set of cipher keys for a cipher algorithm, and a key expansion pipeline comprising a plurality of pipeline stages. During a key expansion mode of operation, each pipeline stage may be configured to perform a corresponding step of generating a member of the expanded set of cipher keys according to a key expansion algorithm. During a cipher mode of operation, a portion of the key expansion pipeline may be configured to perform a step of the cipher algorithm.
摘要翻译： 一种用于加密密钥扩展的装置和方法。 根据第一实施例，密码单元可以包括被配置为存储用于密码算法的扩展密钥集合的密钥存储器和包括多个流水线级的密钥扩展流水线。 在密钥扩展操作模式期间，每个流水线级可以被配置为执行根据密钥扩展算法生成扩展密钥集合的成员的对应步骤。 在密码操作模式期间，密钥扩展流水线的一部分可以被配置为执行密码算法的步骤。
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7.发明授权公开(公告)号：US07620821B1
公开(公告)日：2009-11-17
申请号：US11064595
申请日：2005-02-24
IPC分类号： G06F11/30
CPC分类号： G06F9/3851 , G06F9/3877 , G06F21/72
摘要： A processor including general-purpose and cryptographic functionality, in which cryptographic operations are visible to user-specified software. According to one embodiment, a processor may include instruction execution logic configured to execute instructions specified by a user of the processor, where the instructions are compliant with a general-purpose instruction set architecture. The processor may further include a cryptographic functional unit configured to implement a plurality of cryptographic operations, and further configured to process the cryptographic operations independently of the instruction execution logic. A subset of the instructions may be executable to cause individual ones of the cryptographic operations to be processed by the cryptographic functional unit.
摘要翻译： 包括通用和加密功能的处理器，其中密码操作对于用户指定的软件是可见的。 根据一个实施例，处理器可以包括被配置为执行由处理器的用户指定的指令的指令执行逻辑，其中指令符合通用指令集架构。 处理器还可以包括被配置为实现多个密码操作的密码功能单元，并且还被配置为独立于指令执行逻辑来处理密码操作。 指令的子集可以是可执行的，以使加密功能单元处理各个密码操作。
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公开(公告)号：US20080317244A1
公开(公告)日：2008-12-25
申请号：US12200792
申请日：2008-08-28
IPC分类号： H04L9/06
CPC分类号： H04L9/0625 , H04L2209/12
摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 适于执行数据加密标准的至少一部分的执行单元。 执行单元包括左半输入; 一键输入 和一个表输入。 执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。 执行单元还包括具有两个输入和一个输出的第一个异或运算符。 第一个独占或运算符被配置为接收左半输入和键输入。 执行单元还包括具有两个输入和一个输出的第二个异或运算符。 第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。 执行单元还包括具有两个输入和一个输出的第三个异或运算符。 第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。
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公开(公告)号：US08358780B2
公开(公告)日：2013-01-22
申请号：US13291026
申请日：2011-11-07
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 描述了用于执行包括左半输入的数据加密标准的至少一部分的执行单元; 一键输入 和Table输入，以及被配置为接收Table输入的第一组晶体管，执行表查找和输出数据。 执行单元还包括具有两个输入的第一异或运算符和被配置为接收左半输入和键输入的输出。 执行单元还包括具有两个输入的第二异或运算符和被配置为接收由第一组晶体管输出的数据并且接收第一个异或运算符的输出的输出。 执行单元还包括具有两个输入的第三异或运算符和被配置为接收左半输入和由第一组晶体管输出的数据的输出。
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公开(公告)号：US08073141B2
公开(公告)日：2011-12-06
申请号：US12200792
申请日：2008-08-28
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 适于执行数据加密标准的至少一部分的执行单元。 执行单元包括左半输入; 一键输入 和一个表输入。 执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。 执行单元还包括具有两个输入和一个输出的第一个异或运算符。 第一个独占或运算符被配置为接收左半输入和键输入。 执行单元还包括具有两个输入和一个输出的第二个异或运算符。 第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。 执行单元还包括具有两个输入和一个输出的第三个异或运算符。 第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。
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