公开(公告)号：US20100008460A1

公开(公告)日：2010-01-14

申请号：US12218375

申请日：2008-07-11

申请人： Liang- Zhang ,  Hui Wang ,  Yong Wang

发明人： Liang- Zhang ,  Hui Wang ,  Yong Wang

IPC分类号： H04L7/00

CPC分类号： H04L25/14

摘要： A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.

摘要翻译： 提出了一种用于在多通道高速串行接口上​​执行时钟校准和去偏移的方法和系统。 与单个位通道相关联的多个串行通道收发器中的每一个接收包括训练序列头部模式的第一数据帧。 基于第一数据帧中的每一个，多个串行通道收发器对多个数据帧进行偏移，并产生多个事件信号。 使用多个事件信号，具有第一相位的核心时钟被调整为与最慢位通道相位对准。