专利检索 ap:("Lihang Fan" OR "Nijun Jiang" OR "Rui Wang") AND inv:"Lihang Fan" 第 1 页

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发明公开
COLUMN ARITHMETIC LOGIC UNIT DESIGN FOR DUAL CONVERSION GAIN SENSOR SUPPORTING CORRELATED MULTIPLE SAMPLING AND THREE READOUT PHASE DETECTION AUTOFOCUS 审中-公开

公开(公告)号：US20240098376A1

公开(公告)日：2024-03-21

申请号：US17934196

申请日：2022-09-21

申请人： Lihang Fan , Nijun Jiang , Rui Wang

发明人： Lihang Fan , Nijun Jiang , Rui Wang

IPC分类号： H04N5/243 , H04N5/378

CPC分类号： H04N5/243 , H04N5/378

摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.