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11 条记录 (耗时 0.027 秒)

    Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits
    3.
    发明授权
    Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits 有权
    针对集成电路静态时序分析的芯片变化降额因子设计专用

    公开(公告)号：US08336010B1

    公开(公告)日：2012-12-18

    申请号：US12824191

    申请日：2010-06-27

    申请人： Hongliang Chang ,  Vassilios Gerousis ,  Sireesha Molakalapalli ,  Sachin Shrivastava

    发明人： Hongliang Chang ,  Vassilios Gerousis ,  Sireesha Molakalapalli ,  Sachin Shrivastava

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/504 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.

    摘要翻译： 在本发明的一个实施例中，公开了一种分析关于管芯内工艺变化的电路设计的方法，以产生设计专用的片上变化（DS-OCV）降额因子。 该方法包括使用过程角库在片上变化模式下执行静态时序分析（STA）。 收集前N个关键时序路径的定时信息。 在N个关键定时路径上执行统计静态时序分析（SSTA），其使用以SSTA为特征的定时模型，具有对过程变量的延迟敏感性。 比较两个定时结果，并得出要在STA OCV时序分析中使用的时钟/数据路径的DS-OCV降额因子，以正确说明过程变化的影响。 用户可以选择为路径或路径组指定DS-OCV降额因子，并以减少的运行时间量来实现准确的时序分析报告。

    Static timing analysis with design-specific on chip variation de-rating factors
    4.
    发明授权
    Static timing analysis with design-specific on chip variation de-rating factors 有权
    静态时序分析与设计特定的片上变化降额因素

    公开(公告)号：US08762908B1

    公开(公告)日：2014-06-24

    申请号：US12824194

    申请日：2010-06-27

    申请人： Hongliang Chang ,  Vassilios Gerousis ,  Sireesha Molakalapalli ,  Sachin Shrivastava

    发明人： Hongliang Chang ,  Vassilios Gerousis ,  Sireesha Molakalapalli ,  Sachin Shrivastava

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/504 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.

    摘要翻译： 在本发明的一个实施例中，公开了一种分析关于管芯内工艺变化的电路设计的方法，以产生设计专用的片上变化（DS-OCV）降额因子。 该方法包括使用过程角库在片上变化模式下执行静态时序分析（STA）。 收集前N个关键时序路径的定时信息。 在N个关键定时路径上执行统计静态时序分析（SSTA），其使用以SSTA为特征的定时模型，具有对过程变量的延迟敏感性。 比较两个定时结果，并得出要在STA OCV时序分析中使用的时钟/数据路径的DS-OCV降额因子，以正确说明过程变化的影响。 用户可以选择为路径或路径组指定DS-OCV降额因子，并以减少的运行时间量来实现准确的时序分析报告。

    System and method of computing pin criticalities under process variations for timing analysis and optimization
    7.
    发明授权
    System and method of computing pin criticalities under process variations for timing analysis and optimization 有权
    在时序分析和优化过程中计算引脚临界值的系统和方法

    公开(公告)号：US08151229B1

    公开(公告)日：2012-04-03

    申请号：US11733749

    申请日：2007-04-10

    申请人： Hongliang Chang ,  Oleg Levitsky ,  Nikolay Rubanov ,  Vassilios Gerousis

    发明人： Hongliang Chang ,  Oleg Levitsky ,  Nikolay Rubanov ,  Vassilios Gerousis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, the slack for each timing pin is calculated, wherein each slack is a function of a process random variable. Then, the criticality of each timing pin is determined as the probability of the timing pin having the minimum slack among the slacks in an independent critical set of timing pins. The criticality of each timing pin may then be normalized. By determining the criticalities of the timing pins in a circuit design, a circuit design system may be able to more easily identify portions of the circuit design that need modification for timing and other purposes.

    摘要翻译： 公开了一种用于确定电路设计中每个定时引脚的关键性的系统和方法。 定时引脚的关键是定时引脚在电路设计中最差松弛的路径上的可能性。 根据该方法，计算每个定时针的松弛，其中每个松弛是过程随机变量的函数。 然后，每个定时引脚的临界值被确定为定时引脚在独立关键的定时引脚组中的松弛中具有最小松弛的概率。 然后可以对每个定时引脚的临界值进行归一化。 通过确定电路设计中的定时引脚的关键性，电路设计系统可能能够更容易地识别电路设计中需要针对时序和其他目的进行修改的部分。

    System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis
    8.
    发明授权
    System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权
    用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法

    公开(公告)号：US08015525B2

    公开(公告)日：2011-09-06

    申请号：US12114203

    申请日：2008-05-02

    申请人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031

    摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

    摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。

    SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
    9.
    发明申请
    SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS 有权
    统计静态时序分析中非GAUSSIAN和非线性变量源变化的系统与方法

    公开(公告)号：US20080201676A1

    公开(公告)日：2008-08-21

    申请号：US12114203

    申请日：2008-05-02

    申请人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

    摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。

    System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis
    10.
    发明授权
    System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis 有权
    用于在统计静态时序分析中适应非高斯和非线性变化源的系统和方法

    公开(公告)号：US07293248B2

    公开(公告)日：2007-11-06

    申请号：US11056850

    申请日：2005-02-11

    申请人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.

    摘要翻译： 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。