Method for performing pattern decomposition for a full chip design
    1.
    发明授权
    Method for performing pattern decomposition for a full chip design 有权
    执行全芯片设计模式分解的方法

    公开(公告)号:US08572521B2

    公开(公告)日:2013-10-29

    申请号:US12270498

    申请日:2008-11-13

    IPC分类号: G06F17/50

    CPC分类号: G03F7/70466 G03F1/70

    摘要: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

    摘要翻译: 一种用于将包含要印刷在晶片上的特征的目标图案分解为多个图案的方法。 该方法包括以下步骤:将目标图案分割成多个贴片; 识别每个补丁内的违反最小间距要求的关键特征; 为具有关键特征的多个补丁中的每一个生成关键组图,其中给定补丁的关键组图定义给定补丁内的关键特征的着色方案,并且关键组图识别延伸到相邻补丁中的关键特征 给给定补丁; 为目标模式生成全局关键组图,其中全局关键组图包括多个补丁中的每一个的关键组图,以及延伸到相邻补丁中的特征的标识; 并基于由全局关键组图定义的着色方案着色目标图案。