公开(公告)号：US11815995B1

公开(公告)日：2023-11-14

申请号：US17730633

申请日：2022-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Che-Wei Liang ,  Shuo-Nan Hung ,  Hung-Wei Lu ,  Ming-Cheng Tu

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/0806 ,  G06F11/20 ,  G11C29/04 ,  G06F11/16

CPC classification number: G06F11/1064 ,  G06F11/1666 ,  G06F11/2017 ,  G06F12/0806 ,  G11C29/04 ,  G06F2212/62

Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.