公开(公告)号：US20250123792A1

公开(公告)日：2025-04-17

申请号：US18814575

申请日：2024-08-25

Applicant: MEDIATEK INC.

Inventor： Tsung-Hsin Chen ,  Chin-Wen Liang ,  Wei-Chen Lin ,  Tung-Hung Lin ,  Shih-Yu Huang ,  Chen-Wei Yu

IPC: G06F3/147 ,  G09G3/34

Abstract: A method for handling a display control of a microprocessor in an electronic device includes: receiving a display trigger signal; and controlling a panel device in the electronic device to display a content, in response to the display trigger signal; wherein a central processing unit (CPU) in the electronic device is in a power off state, when controlling the panel device to display the content.

公开(公告)号：US11974071B2

公开(公告)日：2024-04-30

申请号：US17892117

申请日：2022-08-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

CPC classification number: H04N7/013

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US20220408054A1

公开(公告)日：2022-12-22

申请号：US17892117

申请日：2022-08-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US11457173B2

公开(公告)日：2022-09-27

申请号：US17153892

申请日：2021-01-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

公开(公告)号：US20210266495A1

公开(公告)日：2021-08-26

申请号：US17153892

申请日：2021-01-21

Applicant: MEDIATEK INC.

Inventor： Kang-Yi Fan ,  Chin-Wen Liang ,  Chang-Chu Liu ,  Sheng-Hsiang Chang ,  You-Min Yeh

IPC: H04N7/01

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.