公开(公告)号：US20230050400A1

公开(公告)日：2023-02-16

申请号：US17866566

申请日：2022-07-18

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Chung-Min Yang

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a logic die surrounded by a molding compound; a memory die disposed in proximity to the logic die; a plurality of vias around the logic die for electrically connecting the logic die to the memory die. Each of the plurality of vias has an oval shape or a rectangular shape when viewed from above. The vias have a horizontal pitch along a first direction and a vertical pitch along a second direction. The vertical pitch is greater than the horizontal pitch.