公开(公告)号：US20240319782A1

公开(公告)日：2024-09-26

申请号：US18605933

申请日：2024-03-15

Applicant: MEDIATEK Inc.

Inventor： Tse-Chung LI ,  Tai-Ying JIANG ,  Ching-Wen CHEN ,  Shang-Wei CHEN

IPC: G06F1/3296 ,  G06F1/3209

CPC classification number: G06F1/3296 ,  G06F1/3209

Abstract: The processor comprises multiple sub-systems. Each sub-system is configured to generate a voltage switching signal. The processor also comprises a packetizing module coupled to the sub-systems. The packetizing module packetizes multiple voltage switching signals generated by the sub-systems to a packet. The processor also comprises a PMIF (power management interface) configured to receive the packet and output the packet.

公开(公告)号：US20250053220A1

公开(公告)日：2025-02-13

申请号：US18446619

申请日：2023-08-09

Applicant: MEDIATEK INC.

Inventor： Kuan-Wen SU ,  Shu-Ching LIN ,  Chien-Yu LAN ,  Shang-Wei CHEN

IPC: G06F1/3206 ,  G06F1/28 ,  G06F9/30

Abstract: An electronic system is provided. The electronic system includes a processor and a first power management circuit. The processor generates and outputs a first data frame. The first data frame includes at least one first guard bit and a first address. The first power management circuit includes a first register. The first power management circuit receives the first data frame and determines legitimacy of the first address according to the least one first guard bit. In response to that the first address is legal, the power management circuit transmits a first response to the processor and accesses a first region in the first register according to the first address.