Hardware Encoder for Color Data in a 2D Rendering Pipeline

    公开(公告)号:US20230334702A1

    公开(公告)日:2023-10-19

    申请号:US17721660

    申请日:2022-04-15

    CPC classification number: G06T9/00 G06T3/40 G06T1/20

    Abstract: A method includes receiving multiple blocks of pixels of an image, wherein the blocks are to be sequentially encoded using a hardware-encoding pipeline; encoding a first block of the blocks by: generating a first hash to represent the first block; identifying a second hash stored in memory matching the first hash, the second hash (i) representing a second block of the blocks previously processed by the hardware-encoding pipeline and (ii) is associated with a tag corresponding to a placeholder for a second header associated with the second block; passing a copy of the tag through the hardware-encoding pipeline as metadata for the first block; determining that the second header is available; replacing the copy of the tag with the second header to generate a first encoding for the first block, wherein the second header specifies a memory region where a second encoding of the second block is stored.

    Block-Based Random Access Capable Lossless Graphics Asset Compression

    公开(公告)号:US20230334618A1

    公开(公告)日:2023-10-19

    申请号:US17721700

    申请日:2022-04-15

    CPC classification number: G06T3/40 G06T9/00

    Abstract: A method includes determining a sequence for compressing blocks of pixels in an image; compressing the blocks sequentially according to the sequence, wherein a first component of a first block is compressed by: selecting a variable-length mode from supported compression modes to compress the first component of the first block based on: determining that the first block is different from previously-compressed blocks compressed according to the sequence; determining that pixels within the first component are different; and determining that a bit length needed for compressing the first component using the variable-length mode is less than a bit length needed for representing the first component uncompressed; and generating a first compression of the first component of the first block using a symbol width selected based on magnitudes of delta values used for encoding the pixels within the first component of the first block.

    Low-power high throughput hardware decoder with random block access

    公开(公告)号:US11831885B2

    公开(公告)日:2023-11-28

    申请号:US17721687

    申请日:2022-04-15

    CPC classification number: H04N19/176 H04N19/132

    Abstract: A method includes receiving a block comprising pixels; encoding the pixels by: arranging the pixels in a sequence; generating a delta encoding of the pixels, the delta encoding comprising (a) a base value and (b) delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence; generating a symbol mask indicating whether each of the delta values is zero or non-zero; determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values; generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width; generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.

    Low-power High Throughput Hardware Decoder with Random Block Access

    公开(公告)号:US20230336745A1

    公开(公告)日:2023-10-19

    申请号:US17721687

    申请日:2022-04-15

    CPC classification number: H04N19/176 H04N19/132

    Abstract: A method includes receiving a block comprising pixels; encoding the pixels by: arranging the pixels in a sequence; generating a delta encoding of the pixels, the delta encoding comprising (a) a base value and (b) delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence; generating a symbol mask indicating whether each of the delta values is zero or non-zero; determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values; generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width; generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.

    Low-power high throughput hardware decoder with random block access

    公开(公告)号:US11882295B2

    公开(公告)日:2024-01-23

    申请号:US17721687

    申请日:2022-04-15

    CPC classification number: H04N19/176 H04N19/132

    Abstract: A method includes receiving a block comprising pixels; encoding the pixels by: arranging the pixels in a sequence; generating a delta encoding of the pixels, the delta encoding comprising (a) a base value and (b) delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence; generating a symbol mask indicating whether each of the delta values is zero or non-zero; determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values; generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width; generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.

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