公开(公告)号：US20240120928A1

公开(公告)日：2024-04-11

申请号：US18470790

申请日：2023-09-20

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chih-Ping KUO ,  Chi-Hua LI

IPC: H03L7/099

CPC classification number: H03L7/099

Abstract: A synchronizing system includes a phase-locked loop (PLL), first and second network controllers (NCs), a retimer and a processor. The PLL receives a local oscillator (LO) signal, generates and outputs a clock signal and a synchronizing signal. The retimer and the first and second NCs operate according to the clock signal. The first/second NC generates a first/second clock-event signal based on the synchronizing signal. The processor generates a first/second Precision Time Protocol (PTP) signal based on the first/second clock-event signal, and transmits the first/second PTP signal to the first/second NC. The second NC delivers the second PTP signal to first transceivers. The retimer performs retiming on the first PTP signal, and delivers the same to second transceivers. In a master mode, the PLL unit generates the synchronizing signal based on the LO signal and a reference time signal received from a global navigation satellite system (GNSS).