公开(公告)号：US20120174074A1

公开(公告)日：2012-07-05

申请号：US13343361

申请日：2012-01-04

Applicant: Malay GANAI

Inventor： Malay GANAI

IPC: G06F9/44

CPC classification number: G06F8/314 ,  G06F11/3604

Abstract: A computer implemented testing methodology employing a scenario-driven modeling of specific instances of bug patterns that commonly occur in concurrent programs which encodes these instances in an SMT-based symbolic analysis. Such modeling and encoding advantageously allow the symbolic analysis framework to focus on real bugs, thereby allowing effective utilization of resources. Experimentation determined a number of previously unknown bugs in public benchmarks and advantageously scenario-specific modeling and encoding improves the scalability of symbolic technique and, therefore, improves overall quality of concurrency testing.

Abstract translation: 一种计算机实现的测试方法，采用对基于SMT的符号分析中编码这些实例的并发程序中通常发生的错误模式的特定实例的场景驱动建模。 这种建模和编码有利地允许符号分析框架专注于真实的错误，从而允许资源的有效利用。 实验确定了许多以前未知的公共基准测试中的错误，有利的是场景特定的建模和编码改进了符号技术的可扩展性，从而提高了并发测试的整体质量。

公开(公告)号：US20070226666A1

公开(公告)日：2007-09-27

申请号：US11689906

申请日：2007-03-22

Applicant: Malay GANAI ,  Aarti GUPTA

Inventor： Malay GANAI ,  Aarti GUPTA

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.

Abstract translation: 从给定的高级设计生成基于SAT的形式验证的验证友好模型，其中在施工期间执行以下准则：1）不重复使用功能单元和寄存器; 2）最小化使用复用和共享; 3）减少控制步骤的数量; 4）避免管道; 5）从“验证友好”库中选择功能单位; 6）重用操作; 7）进行维护保养切片; 8）在语言规范中支持“假设”和“断言”; 和8）使用外部存储器模块而不是寄存器阵列。

公开(公告)号：US20070226665A1

公开(公告)日：2007-09-27

申请号：US11689803

申请日：2007-03-22

Applicant: Malay GANAI ,  Aarti GUPTA

Inventor： Malay GANAI ,  Aarti GUPTA

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem instances.

Abstract translation: 一种从模型中有效提取高级别信息的加速高级有界模型检查方法，利用提取的信息获取改进的验证模型，并即时应用相关信息，简化BMC问题实例。

公开(公告)号：US20120151271A1

公开(公告)日：2012-06-14

申请号：US13316123

申请日：2011-12-09

Applicant: Malay GANAI

Inventor： Malay GANAI

IPC: G06F11/36

CPC classification number: G06F11/3612 ,  G06F11/3636

Abstract: A computer implemented testing framework for symbolic trace analysis of observed concurrent traces that uses MAT-based reduction to obtain succinct encoding of concurrency constraints, resulting in quadratic formulation in terms of number of transitions. We also present encoding of various violation conditions. Especially, for data races and deadlocks, we present techniques to infer and encode the respective conditions. Our experimental results show the efficacy of such encoding compared to previous encoding using cubic formulation. We provided proof of correctness of our symbolic encoding.

Abstract translation: 计算机实现的用于对观察到的并发跟踪的符号跟踪分析的测试框架，其使用基于MAT的减少来获得并发约束的简洁编码，从而根据转换次数进行二次公式化。 我们还提供各种违规情况的编码。 特别地，对于数据竞争和死锁，我们提出了推断和编码各自条件的技术。 我们的实验结果显示与使用立方体制剂的先前编码相比，这种编码的功效。 我们提供了我们符号编码正确性的证明。

公开(公告)号：US20060282807A1

公开(公告)日：2006-12-14

申请号：US11422069

申请日：2006-06-03

Applicant: Franjo IVANCIC ,  Aarti GUPTA ,  Malay GANAI ,  Himanshu JAIN

Inventor： Franjo IVANCIC ,  Aarti GUPTA ,  Malay GANAI ,  Himanshu JAIN

IPC: G06F17/50

CPC classification number: G06F11/3608

Abstract: A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.

Abstract translation: 公开了用于软件程序的形式验证的系统和方法，其有利地提高了验证系统中的抽象精炼循环的性能。

公开(公告)号：US20110246970A1

公开(公告)日：2011-10-06

申请号：US13075573

申请日：2011-03-30

Applicant: Malay GANAI ,  Chao WANG

Inventor： Malay GANAI ,  Chao WANG

IPC: G06F9/44

CPC classification number: G06F11/3608

Abstract: A method for the verification of multi-threaded computer programs through the use of concurrent trace programs (CTPs) and transaction sequence graphs (TSGs).

Abstract translation: 通过使用并发跟踪程序（CTP）和事务序列图（TSG）来验证多线程计算机程序的方法。

公开(公告)号：US20080281563A1

公开(公告)日：2008-11-13

申请号：US12116668

申请日：2008-05-07

Applicant: Malay GANAI ,  Aarti GUPTA

Inventor： Malay GANAI ,  Aarti GUPTA

IPC: G06G7/62 ,  G06F17/10

CPC classification number: G06F11/3608 ,  G06F17/504

Abstract: A computer implemented method for modeling and verifying concurrent systems which uses Satisfiability-Modulo Theory (SMT)-based Bounded Model Checking (BMC) to detect violations of safety properties such as data races. A particularly distinguishing aspect of our inventive method is that we do not introduce wait-cycles in our symbolic models for the individual threads, which are typically required for considering an interleaved execution of the threads. These wait-cycles are detrimental to the performance of BMC. Instead, we first create independent models for the different threads, and add inter-model constraints lazily, incrementally, and on-the-fly during BMC unrolling to capture the sequential consistency and synchronization semantics. We show that our constraints provide a sound and complete modeling with respect to the considered semantics. One benefit of our lazy modeling method is the reduction in the size of the BMC problem instances, thereby, improving the verification performance in both runtime and memory.

Abstract translation: 一种用于建模和验证并发系统的计算机实现方法，其使用基于可信性 - 模理论（SMT）的有界模型检查（BMC）来检测诸如数据竞赛之类的安全属性的违规。 我们的创造性方法的特别区别在于，我们不在针对各个线程的符号模型中引入等待周期，这通常是考虑线程的交错执行所需要的。 这些等待周期对BMC的性能是不利的。 相反，我们首先为不同的线程创建独立的模型，并在BMC展开期间懒洋洋地，逐步地和即时地添加模型间约束，以捕获顺序一致性和同步语义。 我们显示我们的约束提供了一个关于所考虑的语义的完整的建模。 我们的懒惰建模方法的一个好处是减少了BMC问题实例的大小，从而提高了运行时和内存中的验证性能。