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公开(公告)号:US06366147B2
公开(公告)日:2002-04-02
申请号:US09874866
申请日:2001-06-04
申请人: Manoj Sachdev , Siva Narenda
发明人: Manoj Sachdev , Siva Narenda
IPC分类号: H03K3289
CPC分类号: H03K3/356156 , H03K3/356121
摘要: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.