公开(公告)号：US07009425B1

公开(公告)日：2006-03-07

申请号：US10778635

申请日：2004-02-13

申请人： Marc J Loinaz ,  Arnold R. Feldman

发明人： Marc J Loinaz ,  Arnold R. Feldman

IPC分类号： H03K17/16

CPC分类号： H03K3/356139 ,  H03K3/012 ,  H03K19/01707

摘要： A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

摘要翻译： 逻辑电路采用并联峰值技术来增强电路的开关速度，而不增加功耗。 差分逻辑门实现数字电路功能。 分流峰值逻辑电路包括两个电阻和两个电感元件。 对于每个差分输出线，电阻元件串联耦合到电感元件，以将电路电源电压耦合到差分输出线。 在这种配置下，逻辑电路的带宽增加，而不增加功耗。 逻辑电路可以使用CML或ECL逻辑来实现。 还公开了用于提高主动分流峰值电路的大信号性能的技术。