Secure booting of an electronic apparatus with SMP architecture
    1.
    发明申请
    Secure booting of an electronic apparatus with SMP architecture 有权
    使用SMP架构安全启动电子设备

    公开(公告)号:US20070113088A1

    公开(公告)日:2007-05-17

    申请号:US11432727

    申请日:2006-05-11

    Applicant: Marcus Volp

    Inventor: Marcus Volp

    CPC classification number: G06F21/575 G06F9/4405 G06F15/177

    Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

    Abstract translation: 在第一处理器的操作系统引导之前,SMP架构设备的安全引导的方法提供了包括第一处理器和共享存储器的一部分的安全域的形成。 第二处理器的操作系统仅在与第一处理器的相互认证之后被引导,并且在认证的情况下,将安全域的扩展到第二处理器。

    Privileged execution context restricting use of hardware resources by other execution contexts
    2.
    发明授权
    Privileged execution context restricting use of hardware resources by other execution contexts 有权
    特权执行上下文限制其他执行上下文使用硬件资源

    公开(公告)号:US07730544B2

    公开(公告)日:2010-06-01

    申请号:US10959716

    申请日:2004-10-06

    Applicant: Marcus Volp

    Inventor: Marcus Volp

    CPC classification number: G06F12/1036 G06F9/3851 G06F2212/656

    Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.

    Abstract translation: 处理器架构提供至少两个同时执行上下文,具有至少一个执行单元的硬件资源,指令调度器,中断控制器和存储器管理装置,以及在特权的同时执行上下文中的给定特权上下文 操作系统的模式,通过读取和写入其他上下文的寄存器来命令其他处理器上下文。

    Secure booting of an electronic apparatus with SMP architecture
    3.
    发明授权
    Secure booting of an electronic apparatus with SMP architecture 有权
    使用SMP架构安全启动电子设备

    公开(公告)号:US07624261B2

    公开(公告)日:2009-11-24

    申请号:US11432727

    申请日:2006-05-11

    Applicant: Marcus Volp

    Inventor: Marcus Volp

    CPC classification number: G06F21/575 G06F9/4405 G06F15/177

    Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

    Abstract translation: 在第一处理器的操作系统引导之前,SMP架构设备的安全引导的方法提供了包括第一处理器和共享存储器的一部分的安全域的形成。 第二处理器的操作系统仅在与第一处理器的相互认证之后被引导,并且在认证的情况下,将安全域的扩展到第二处理器。

    Memory access control in an electronic apparatus
    4.
    发明申请
    Memory access control in an electronic apparatus 审中-公开
    电子设备中的存储器访问控制

    公开(公告)号:US20050182909A1

    公开(公告)日:2005-08-18

    申请号:US11022284

    申请日:2004-12-22

    CPC classification number: G06F12/1458

    Abstract: A method of access control in an electronic apparatus comprising at least one device and a shared memory, external to the said devices, which are connected by at least one communication bus. In one embodiment, a memory access control unit receives an instruction for access to the memory. The validity of the received operation is verified. If it is valid, the operation is carried out. Otherwise, the operation is not executed and no corresponding signal or instruction is produced. In response to invalid read operations, dummy data may be returned. This “silent” blocking of the operation makes it possible to control devices with DMA capability.

    Abstract translation: 一种电子设备中的访问控制方法,包括由至少一个通信总线连接的至少一个设备和所述设备外部的共享存储器。 在一个实施例中,存储器访问控制单元接收访问存储器的指令。 验证接收到的操作的有效性。 如果有效,则执行操作。 否则,不执行操作,不产生相应的信号或指令。 响应于无效的读取操作,可以返回虚拟数据。 这种“无声”的操作阻塞使得可以控制具有DMA能力的设备。

    Multicontext processor architecture
    6.
    发明申请
    Multicontext processor architecture 有权
    多文字处理器架构

    公开(公告)号:US20050081020A1

    公开(公告)日:2005-04-14

    申请号:US10959716

    申请日:2004-10-06

    Applicant: Marcus Volp

    Inventor: Marcus Volp

    CPC classification number: G06F12/1036 G06F9/3851 G06F2212/656

    Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.

    Abstract translation: 处理器架构提供至少两个同时执行上下文,具有至少一个执行单元的硬件资源,指令调度器,中断控制器和存储器管理装置,以及在特权的同时执行上下文中的给定特权上下文 操作系统的模式,通过读取和写入其他上下文的寄存器来命令其他处理器上下文。

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