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公开(公告)号：US11567767B2
公开(公告)日：2023-01-31
申请号：US16944141
申请日：2020-07-30
申请人： Marvell Asia Pte, Ltd. , Cray Inc.
发明人： Harold Wade Cain, III , Rabin Andrew Sugumar , Nagesh Bangalore Lakshminarayana , Daniel Jonathan Ernst , Sanyam Mehta
摘要： A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.
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公开(公告)号：US20220035632A1
公开(公告)日：2022-02-03
申请号：US16944141
申请日：2020-07-30
发明人： Harold Wade Cain, III , Rabin Andrew Sugumar , Nagesh Bangalore Lakshminarayana , Daniel Jonathan Ernst , Sanyam Mehta
IPC分类号： G06F9/30
摘要： A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.
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