System for identification of defects on circuits or other arrayed products
    1.
    发明授权
    System for identification of defects on circuits or other arrayed products 有权
    用于识别电路或其他阵列产品上的缺陷的系统

    公开(公告)号:US07346470B2

    公开(公告)日:2008-03-18

    申请号:US10459132

    申请日:2003-06-10

    IPC分类号: G06F15/00 G06F17/50

    CPC分类号: H01L22/20

    摘要: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

    摘要翻译: 公开了一种用于评估半导体晶片的操作失败概率的系统和方法。 该方法包括将危险因素数据输入存储器并将多个晶片输入到半导体制造制造过程中。 选择晶片的子集以获得样本群体,并且检查样本群体的每个晶片的至少一个区域。 获得与样品群的每个晶片相关联的电路设计数据,并且识别出对特定晶片的操作具有增加的风险的一个或多个缺陷。 识别是风险因素数据,检查步骤和电路设计数据的函数。 计算半导体晶片故障的概率。

    Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products
    2.
    发明申请
    Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products 审中-公开
    用于识别电路或其他阵列产品缺陷的设计结构和系统

    公开(公告)号:US20080148201A1

    公开(公告)日:2008-06-19

    申请号:US11969294

    申请日:2008-01-04

    IPC分类号: G06F17/50

    CPC分类号: H01L22/20

    摘要: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

    摘要翻译: 公开了一种用于评估半导体晶片的操作失败概率的系统和方法。 该方法包括将危险因素数据输入存储器并将多个晶片输入到半导体制造制造过程中。 选择晶片的子集以获得样本群体,并且检查样本群体的每个晶片的至少一个区域。 获得与样品群的每个晶片相关联的电路设计数据,并且识别出对特定晶片的操作具有增加的风险的一个或多个缺陷。 识别是风险因素数据,检查步骤和电路设计数据的函数。 计算半导体晶片故障的概率。

    Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products
    3.
    发明申请
    Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products 有权
    用于识别电路或其他阵列产品缺陷的设计结构和系统

    公开(公告)号:US20080092095A1

    公开(公告)日:2008-04-17

    申请号:US11926605

    申请日:2007-10-29

    IPC分类号: G06F17/50

    摘要: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

    摘要翻译: 公开了一种用于评估半导体晶片的操作失败概率的系统和方法。 该方法包括将危险因素数据输入存储器并将多个晶片输入到半导体制造制造过程中。 选择晶片的子集以获得样本群体,并且检查样本群体的每个晶片的至少一个区域。 获得与样品群的每个晶片相关联的电路设计数据,并且识别出对特定晶片的操作具有增加的风险的一个或多个缺陷。 识别是风险因素数据,检查步骤和电路设计数据的函数。 计算半导体晶片故障的概率。

    Design structure and system for identification of defects on circuits or other arrayed products
    4.
    发明授权
    Design structure and system for identification of defects on circuits or other arrayed products 有权
    用于识别电路或其他阵列产品上的缺陷的设计结构和系统

    公开(公告)号:US07752581B2

    公开(公告)日:2010-07-06

    申请号:US11926605

    申请日:2007-10-29

    IPC分类号: G06F17/50

    摘要: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

    摘要翻译: 公开了一种用于评估半导体晶片的操作失败概率的系统和方法。 该方法包括将危险因素数据输入存储器并将多个晶片输入到半导体制造制造过程中。 选择晶片的子集以获得样本群体,并且检查样本群体的每个晶片的至少一个区域。 获得与样品群的每个晶片相关联的电路设计数据,并且识别出对特定晶片的操作具有增加的风险的一个或多个缺陷。 识别是风险因素数据,检查步骤和电路设计数据的函数。 计算半导体晶片故障的概率。

    System for identification of defects on circuits or other arrayed products
    5.
    发明申请
    System for identification of defects on circuits or other arrayed products 审中-公开
    用于识别电路或其他阵列产品上的缺陷的系统

    公开(公告)号:US20060265185A1

    公开(公告)日:2006-11-23

    申请号:US11493092

    申请日:2006-07-25

    IPC分类号: G06F17/18

    CPC分类号: H01L22/20

    摘要: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

    摘要翻译: 公开了一种用于评估半导体晶片的操作失败概率的系统和方法。 该方法包括将危险因素数据输入存储器并将多个晶片输入到半导体制造制造过程中。 选择晶片的子集以获得样本群体,并且检查样本群体的每个晶片的至少一个区域。 获得与样品群的每个晶片相关联的电路设计数据,并且识别出对特定晶片的操作具有增加的风险的一个或多个缺陷。 识别是风险因素数据,检查步骤和电路设计数据的函数。 计算半导体晶片故障的概率。