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5 条记录 (耗时 0.017 秒)

    Connector structure
    1.
    发明授权
    Connector structure 失效
    连接器结构

    公开(公告)号：US4806111A

    公开(公告)日：1989-02-21

    申请号：US925904

    申请日：1986-11-03

    申请人： Masaaki Nishi ,  Moritoshi Yasunaga ,  Ryotaro Kamikawai

    发明人： Masaaki Nishi ,  Moritoshi Yasunaga ,  Ryotaro Kamikawai

    IPC分类号： H01R4/02 ,  H01R13/03 ,  H01R3/00

    CPC分类号： H01R23/6873 ,  H01R13/03 ,  H01R4/028 ,  Y10S439/931

    摘要： A connector structure comprising an electrically conductive plate having a plurality of through holes formed therein, an electrically insulated film formed on the inner wall of at least one of the through holes, an electrically conductive film formed on the inner wall of at least one other through hole, and an electrically conductive material of a low melting point provided within the through holes. The low melting point material provided in the through holes whose inner walls are coated with an electrically insulating film is insulated from the electrically conductive plate and such through holes may serve to receive signal propagating pins. The low melting point material in the through holes whose inner walls are coated with an electrically conductive film are tightly bonded to its inner wall due to the wettability between the low melting point material and the electrically conductive film so that such through holes may serve to receive a common potential pin to electrically stabilize the electrically conductive plate and to reduce electrical capacitance unnecessarily formed between the signal propagating pin receiving through holes. Thus, the connector structure is adapted for a high speed signal transmission without suffering substantial crosstalk noise.

    摘要翻译： 一种连接器结构，包括具有形成在其中的多个通孔的导电板，形成在至少一个通孔的内壁上的电绝缘膜，形成在内壁上的至少一个其它通孔 孔，以及设置在通孔内的低熔点导电材料。 设置在其内壁涂有电绝缘膜的通孔中的低熔点材料与导电板绝缘，并且这种通孔可用于接收信号传播销。 内壁涂有导电膜的通孔中的低熔点材料由于低熔点材料和导电膜之间的润湿性而紧密地结合到其内壁，使得这样的通孔可以用于接收 用于使导电板电稳定并且减少在信号传播销接收通孔之间不必要地形成的电容的公共电位引脚。 因此，连接器结构适用于高速信号传输，而不会产生实质的串扰噪声。

    Clock signal supply system
    2.
    发明授权
    Clock signal supply system 失效
    时钟信号供电系统

    公开(公告)号：US5184027A

    公开(公告)日：1993-02-02

    申请号：US688696

    申请日：1991-04-22

    申请人： Noboru Masuda ,  Ryotaro Kamikawai ,  Masayoshi Yagyu ,  Masakazu Yamamoto ,  Hiroyuki Itoh ,  Tatsuya Saito

    发明人： Noboru Masuda ,  Ryotaro Kamikawai ,  Masayoshi Yagyu ,  Masakazu Yamamoto ,  Hiroyuki Itoh ,  Tatsuya Saito

    IPC分类号： C04B35/45 ,  G06F1/10 ,  H01L39/12 ,  H01L39/24

    CPC分类号： C04B35/4504 ,  G06F1/10 ,  H01L39/126 ,  H01L39/2419

    摘要： A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.

    摘要翻译： 时钟信号供应系统提供时钟信号的自动精确相位调整。 该系统包括产生时钟信号的振荡器和产生相对于由振荡器产生的时钟信号具有预定关系的参考信号的参考发生器。 在要接收时钟信号的每个位置，提供调整电路以调整所接收的时钟信号的相位。 这种调整电路可以包括可变延迟电路，其接收时钟信号并且产生由具有变化的延迟的时钟信号构成的输出到连接电路的其余部分。 此外，可变延迟的输出被反馈到相位差检测电路。 参考信号是相位差检测电路的第二输入。 该相位差检测电路比较参考信号和可变延迟电路的输出的差异，并将该控制信号产生到可变延迟电路，该可变延迟电路将进一步调节所接收的时钟信号的相位。 该调整是在要接收时钟信号的每个位置处执行的，从而提供对时钟信号的相位的自动调整。

    Superconducting logic circuit
    3.
    发明授权
    Superconducting logic circuit 失效
    超导逻辑电路

    公开(公告)号：US5151617A

    公开(公告)日：1992-09-29

    申请号：US665085

    申请日：1991-03-06

    申请人： Eiichi Goto ,  Willy Hioe ,  Mutsumi Hosoya ,  Ryotaro Kamikawai

    发明人： Eiichi Goto ,  Willy Hioe ,  Mutsumi Hosoya ,  Ryotaro Kamikawai

    IPC分类号： H03K19/195

    CPC分类号： H03K19/1952 ,  Y10S505/859

    摘要： A superconducting logic circuit is configured by using two kinds of input-output type quantum flux parametrons (QFP), that is, a periodically excited input-output type QFP and an arbitrarily excited input-output type QFP. The periodically excited QFP is excited by periodically varying exciting magnetic flux to amplify a binary magnetic flux. The arbitrarily excited QFP is excited by magnetic flux output signals of upstream QFPs.

    摘要翻译： 通过使用两种输入输出型量子通量参量（QFP），即周期性激励的输入输出型QFP和任意激励的输入输出型QFP来配置超导逻辑电路。 周期性激发的QFP通过周期性地改变激发磁通来放大二进制磁通量来激发。 任意激发的QFP由上游QFP的磁通量输出信号激发。

    Stacked differentially driven transmission line on integrated circuit
    4.
    发明授权
    Stacked differentially driven transmission line on integrated circuit 失效
    集成电路上堆叠的差分驱动传输线

    公开(公告)号：US4626889A

    公开(公告)日：1986-12-02

    申请号：US682938

    申请日：1984-12-18

    申请人： Masakazu Yamamoto ,  Akira Masaki ,  Ryotaro Kamikawai

    发明人： Masakazu Yamamoto ,  Akira Masaki ,  Ryotaro Kamikawai

    IPC分类号： H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01L23/64 ,  H01P3/08 ,  H01P3/18

    CPC分类号： H01L23/64 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A semiconductor integrated circuit structure including a semiconductor substrate having a large area adapted for a large scale integration, a circuit formed in the substrate for generating a pair of complementary signals, a pair of common potential level layers with an electrically insulating layer interposed therebetween, the common potential level layers being formed above and being electrically insulated from the substrate, and a pair of electric conductor pattern layers formed in the insulating layer for conducting the pair of complementary signals. The electric conductor pattern layers are arranged so as to be overlapped with each other in a direction substantially perpendicular to the large area substrate and so as to be substantially parallel with the large area substrate. The overall length of the electric conductor pattern layers is such that when an electric signal is conducted through an electric conductor in an IC having a length equal to the above-mentioned overall length, attenuation of the signal thereby is not negligible.

    摘要翻译： 一种半导体集成电路结构，包括具有适合于大规模集成的大面积的半导体衬底，形成在用于产生一对互补信号的衬底中的电路，一对具有介于其间的电绝缘层的公共电位电平层， 公共电位层形成在上方并与衬底电绝缘，以及一对电导体图案层，形成在绝缘层中，用于引导该对互补信号。 电导体图案层被布置成在与大面积基板大致垂直的方向上彼此重叠，并且与大面积基板大致平行。 电导体图形层的总长度使得当电信号通过长度等于上述总长度的IC中的导电体传导时，信号的衰减不可忽略。