公开(公告)号：US5243628A

公开(公告)日：1993-09-07

申请号：US676191

申请日：1991-03-27

申请人： Masakazu Moritoki ,  Masao Hagiware

发明人： Masakazu Moritoki ,  Masao Hagiware

IPC分类号： H03M5/06 ,  H03M5/14 ,  H04L25/48 ,  H04L25/49

CPC分类号： H03M5/06 ,  H03M5/14 ,  H04L25/4908

摘要： A novel encoding method which facilitates handling at the time of demodulation (decoding) and is capable of further alleviating a burden imposed on a demodulation (decoding) circuit. When an input NRZ code signal is at, for instance, a logical "0" level during a given unit bit time, encoding is effected to obtain a signal having the same form as that of a CMI code such that the signal is set to a logical "1" level in correspondence with a first half of the unit bit time, and to the logical "0" level in correspondence with a second half thereof. Similarly, when the input NRZ code signal is at the logical "1" level during a given unit bit time, encoding is effected to obtain a signal such that the signal is unfailingly set to the logical "1" level during its initial bit time, and thereafter only during a bit time when the NRZ code signal is at the logical "1" level during the unit bit time, the logical "1" level and the logical "0" level are alternately repeated for each unit bit time. By virtue of this encoding, a maximum interval between adjacent signal rise or fall timings is reduced to a bit time of two bits.

摘要翻译： 一种便于在解调（解码）时的处理并且能够进一步减轻对解调（解码）电路的负担的新型编码方法。 当输入NRZ码信号在给定的单位比特时间期间处于例如逻辑“0”电平时，进行编码以获得具有与CMI码相同形式的信号，使得该信号被设置为 逻辑“1”电平，并且与其第二半部对应的逻辑“0”电平。 类似地，当在给定的单位比特时间期间输入的NRZ码信号处于逻辑“1”电平时，进行编码以获得信号，使得信号在其初始比特时间内始终设置为逻辑“1”电平， 此后仅在NRZ码信号在单位比特时间期间处于逻辑“1”电平的位时间期间，对于每个单位比特时间，逻辑“1”电平和逻辑“0”电平交替重复。 由于这种编码，相邻信号上升或下降定时之间的最大间隔减少到两位的位时间。