公开(公告)号：US5172378A

公开(公告)日：1992-12-15

申请号：US520644

申请日：1990-05-08

申请人： Masayuki Sugioka ,  Yoshikazu Mori ,  Hiroyuki Hidaka ,  Fumio Enmei

发明人： Masayuki Sugioka ,  Yoshikazu Mori ,  Hiroyuki Hidaka ,  Fumio Enmei

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/22 ,  G06F11/0751 ,  G06F2201/865

摘要： In an information processor having a central processing unit, a main storage which is accessed by the central processing unit, and an input/output processing unit which controls transfer of information between the central processing unit as well as the main storage and exterior of the information processor; a memory area of the main storage is partitioned into a software area and a hardware area, a train of instructions for inspecting the central processing unit, the main storage and the input/output processing unit are stored in the hardware area, and the central processing unit executes a program stored in the software area and the instruction train stored in the hardware area, alternately at desired intervals so as to decide existence or nonexistence of occurrence of an error on the basis of an executed result of the instruction train.

摘要翻译： 在具有中央处理单元的信息处理器，由中央处理单元访问的主存储器以及控制中央处理单元之间的信息的传送以及信息的主存储和外部的输入/输出处理单元 处理器; 将主存储器的存储区域划分为软件区域和硬件区域，用于检查中央处理单元，主存储器和输入/输出处理单元的一系列指令被存储在硬件区域中，并且中央处理 单元以期望的间隔交替地执行存储在软件区域和存储在硬件区域中的指令序列的程序，以便基于指令序列的执行结果来决定是否存在错误的发生。