Method and apparatus for sequencing misaligned external bus transactions
in which the order of completion of corresponding split transaction
requests is guaranteed
    1.
    发明授权
    Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed 失效
    用于对未对准的外部总线事务进行排序的方法和装置,其中保证相应的分批交易请求的完成顺序

    公开(公告)号:US5535345A

    公开(公告)日:1996-07-09

    申请号:US241964

    申请日:1994-05-12

    IPC分类号: G06F15/17 H01J13/00

    CPC分类号: G06F15/17

    摘要: In accordance with the preferred embodiment of the present invention, a bus interface unit of a microprocessor is provided with a Micro Request Sequencer (EBMRS) disposed between a bus scheduling queue (EBBQ) and external bus control logic (EBCTL). Under normal bus request traffic, the EBMRS is effectively transparent and allows normal communication between the EBCTL and the EBBQ. However, for misaligned bus transactions, which comprise memory accesses that cross a bus width boundary, the EBMRS intercepts such transactions for special sequencing, while blocking any further requests from the EBBQ. The EBMRS separates each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus. It then issues the first split request to the EBCTL for processing on the external bus. External bus agents involved with processing of the split requests then return first response information regarding the completion of the first split request. If the first response information indicates that the first split request will complete without being deferred or retried, the EBMRS issues the second split request to the EBCTL for processing on the external bus. Upon the receipt of second response information for the second split request indicating that the second split request is guaranteed to complete without being deferred or retried, the EBMRS then issues any further transaction requests received from the EBBQ without jeopardizing the order dependency of the split requests or subsequent bus transaction requests buffered in the EBBQ.

    摘要翻译: 根据本发明的优选实施例,微处理器的总线接口单元设置有布置在总线调度队列(EBBQ)和外部总线控制逻辑(EBCTL)之间的微请求排序器(EBMRS)。 在正常总线请求流量下,EBMRS有效透明,允许EBCTL和EBBQ之间进行正常通信。 然而,对于包含跨越总线宽度边界的存储器访问的未对齐总线事务,EBMRS拦截这种事务以进行特殊排序,同时阻止来自EBBQ的任何进一步的请求。 EBMRS将每个不对齐的总线事务请求分成至少第一和第二分组事务请求,每个分离请求形成不跨越外部总线的数据总线宽度边界的存储器访问。 然后,它向EBCTL发出第一个分离请求,以在外部总线上进行处理。 涉及处理分离请求的外部总线代理然后返回关于完成第一个分离请求的第一响应信息。 如果第一个响应信息指示第一个分离请求将在不延迟或重试的情况下完成,则EBMRS向EBCTL发出第二个分离请求以在外部总线上进行处理。 在接收到指示第二分裂请求被保证完成而不被延迟或重试的第二分组请求的第二响应信息时,EBMRS然后发出从EBBQ接收的任何进一步的事务请求,而不会危害分离请求的顺序依赖性, 在EBBQ中缓存的后续总线事务请求。