公开(公告)号：US08689156B2

公开(公告)日：2014-04-01

申请号：US13779457

申请日：2013-02-27

Applicant: Maxeler Technologies Ltd.

Inventor： James Huggett ,  Jacob Alexis Bower ,  Oliver Pell

IPC: G06F17/50

CPC classification number: G06F9/30079 ,  G06F17/5054

Abstract: A method of generating a hardware design for a pipelined parallel stream processor. The method includes defining a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor and defining a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles. The method also includes defining the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities, collectively solving the set of linear inequalities for the entire graph, optimizing the at least one data path in the graph using the solved linear inequalities to produce an optimized graph, and utilizing the optimized graph to define an optimized hardware design for implementation in hardware as the pipelined parallel stream processor.

Abstract translation: 一种为流水线并行流处理器生成硬件设计的方法。 该方法包括定义处理操作，指定要在硬件中实现的处理，作为所述流水线并行流处理器的一部分，并且将表示所述处理操作的图形定义为时域中的并行结构，作为时钟周期的函数。 该方法还包括将所述图形的至少一个数据路径和相关联的延迟定义为一组代数线性不等式，共同地解决整个图形的线性不等式集合，使用求解的图来优化图中的至少一个数据路径 线性不等式以产生优化的图，并且利用优化的图来定义用于在硬件中实现的优化的硬件设计作为流水线并行流处理器。