公开(公告)号：US20170063358A1

公开(公告)日：2017-03-02

申请号：US15243237

申请日：2016-08-22

Applicant: MediaTek Inc.

Inventor： Yi-Feng CHEN ,  Ya-Shih HUANG ,  Chun-Sheng HUANG ,  Yiwei CHEN

IPC: H03K5/15

CPC classification number: H03K5/15 ,  H03K5/135 ,  H03K2005/00019

Abstract: A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

Abstract translation: 提供时钟缓冲电路。 时钟缓冲电路接收输入时钟信号并产生延迟时钟信号。 时钟缓冲电路包括输入电路，输出电路，第一延迟路径和第二延迟路径。 输入电路接收输入时钟信号，并根据输入时钟信号产生输出时钟信号。 输出电路产生延迟时钟信号。 第一延迟路径耦合在输入电路和输出电路之间。 第二延迟路径耦合在输入电路和输出电路之间。 输入电路根据控制信号选择性地将输出时钟信号提供给第一和第二延迟路径中的第一特定延迟路径。 输出电路接收通过第一特定延迟路径的输出时钟信号并输出​​延迟时钟信号。