公开(公告)号：US10171103B1

公开(公告)日：2019-01-01

申请号：US15870161

申请日：2018-01-12

Applicant: Mellanox Technologies Ltd.

Inventor： Adir Zevulun ,  Noam Rom ,  Nir Shmuel

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

Abstract: A hardware compression architecture including a shift register including: a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage; a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match; logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.