公开(公告)号：US06988173B2

公开(公告)日：2006-01-17

申请号：US10435878

申请日：2003-05-12

申请人： Michael A. Blake ,  Steven M. German ,  Pak-kin Mak ,  Adrian E. Seigler ,  Gary A. Van Huben

发明人： Michael A. Blake ,  Steven M. German ,  Pak-kin Mak ,  Adrian E. Seigler ,  Gary A. Van Huben

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.

摘要翻译： 公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。 节点通过双同心环拓扑互连。 总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。 每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。 该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。 总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

公开(公告)号：US08473883B2

公开(公告)日：2013-06-25

申请号：US13197061

申请日：2011-08-03

申请人： Steven M. German

发明人： Steven M. German

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504

摘要： The illustrative embodiments provide a mechanism for abstraction for arrays in integrated circuit designs. The mechanism constructs abstract models directly from an analysis of the system. The abstract models are both sound and complete for safety properties: a safety property holds in the abstract model if and only if the property holds in the original model. The mechanism of the illustrative embodiments eliminates the need for iterative abstraction refinement. The mechanism of the illustrative embodiments can find small models that verify a system in some cases where other approaches are unable to find a small model. The approach constructs an abstract design from the original design. The abstracted design may have smaller arrays than the original design. The mechanism checks the correctness of the abstracted design by model checking.

摘要翻译： 说明性实施例为集成电路设计中的阵列提供抽象的机制。 该机制直接从系统分析中构建抽象模型。 抽象模型对于安全属性是完整的和完整的：当且仅当属性在原始模型中保持时，抽象模型中才有一个安全属性。 说明性实施例的机制消除了迭代抽象改进的需要。 说明性实施例的机制可以找到在其他方法不能找到小型模型的某些情况下验证系统的小型模型。 该方法从原始设计构建抽象设计。 抽象的设计可能具有比原始设计更小的阵列。 该机制通过模型检查来检查抽象设计的正确性。

公开(公告)号：US20130036391A1

公开(公告)日：2013-02-07

申请号：US13197061

申请日：2011-08-03

申请人： Steven M. German

发明人： Steven M. German

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： The illustrative embodiments provide a mechanism for abstraction for arrays in integrated circuit designs. The mechanism constructs abstract models directly from an analysis of the system. The abstract models are both sound and complete for safety properties: a safety property holds in the abstract model if and only if the property holds in the original model. The mechanism of the illustrative embodiments eliminates the need for iterative abstraction refinement. The mechanism of the illustrative embodiments can find small models that verify a system in some cases where other approaches are unable to find a small model. The approach constructs an abstract design from the original design. The abstracted design may have smaller arrays than the original design. The mechanism checks the correctness of the abstracted design by model checking.

摘要翻译： 说明性实施例为集成电路设计中的阵列提供抽象的机制。 该机制直接从系统分析中构建抽象模型。 抽象模型对于安全属性是完整的和完整的：当且仅当属性在原始模型中保持时，抽象模型中才有一个安全属性。 说明性实施例的机制消除了迭代抽象改进的需要。 说明性实施例的机制可以找到在其他方法不能找到小型模型的某些情况下验证系统的小型模型。 该方法从原始设计构建抽象设计。 抽象的设计可能具有比原始设计更小的阵列。 该机制通过模型检查来检查抽象设计的正确性。