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    PRE-SCHEDULED REPLAYS OF DIVERGENT OPERATIONS
    1.
    发明申请
    PRE-SCHEDULED REPLAYS OF DIVERGENT OPERATIONS 审中-公开
    预先安排的重复操作

    公开(公告)号：US20130212364A1

    公开(公告)日：2013-08-15

    申请号：US13370173

    申请日：2012-02-09

    申请人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Jack Hilaire Choquette ,  Shirish Gadre ,  Olivier Giroux ,  Douglas J. Hahn ,  Steven James Heinrich ,  Eric Lyell Hill ,  Charles McCarver ,  Omkar Paranjape ,  Anjana Rajendran ,  Rajeshwaran Selvanesan

    发明人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Jack Hilaire Choquette ,  Shirish Gadre ,  Olivier Giroux ,  Douglas J. Hahn ,  Steven James Heinrich ,  Eric Lyell Hill ,  Charles McCarver ,  Omkar Paranjape ,  Anjana Rajendran ,  Rajeshwaran Selvanesan

    IPC分类号： G06F9/38 ,  G06F9/312

    CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3887

    摘要： One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency.

    摘要翻译： 本公开的一个实施例阐述了在并行处理子系统中执行用于发散操作的预先安排的重播操作的优化方式。 具体地，流式多处理器（SM）包括多级流水线，其被配置为将预先安排的重播操作插入到多级流水线中。 预先安排的重播单元检测与当前指令相关联的操作是否正在访问公共资源。 如果线程正在访问分布在多个高速缓存线上的数据，则预先安排的重播单元在当前指令后面插入预先安排的重放操作。 多级流水线顺序执行指令和相关的预先安排的重播操作。 如果附加线程在执行指令和预先安排的重放操作之后保持未被接受，则通过重放循环插入附加的重放操作，直到对所有线程进行服务。 所公开技术的一个优点是需要一个或多个重放操作的发散操作以较低的等待时间执行。

    MECHANISM FOR TRACKING AGE OF COMMON RESOURCE REQUESTS WITHIN A RESOURCE MANAGEMENT SUBSYSTEM
    4.
    发明申请
    MECHANISM FOR TRACKING AGE OF COMMON RESOURCE REQUESTS WITHIN A RESOURCE MANAGEMENT SUBSYSTEM 有权
    跟踪资源管理子系统中共同资源年龄的机制

    公开(公告)号：US20130311686A1

    公开(公告)日：2013-11-21

    申请号：US13476825

    申请日：2012-05-21

    申请人： Michael FETTERMAN ,  Shirish Gadre ,  John H. Edmondson ,  Omkar Paranjape ,  Anjana Rajendran ,  Eric Lyell Hill ,  Rajeshwaran Selvanesan ,  Charles McCarver ,  Kevin Mitchell ,  Steven James Heinrich

    发明人： Michael FETTERMAN ,  Shirish Gadre ,  John H. Edmondson ,  Omkar Paranjape ,  Anjana Rajendran ,  Eric Lyell Hill ,  Rajeshwaran Selvanesan ,  Charles McCarver ,  Kevin Mitchell ,  Steven James Heinrich

    IPC分类号： G06F5/00

    CPC分类号： H04L49/254 ,  G06F9/46

    摘要： One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.

    摘要翻译： 本公开的一个实施例阐述了在与重放操作相关的公共资源访问请求的调度中维持公平性和顺序的有效方式。 具体地说，流式多处理器（SM）包括配置成通过一个或多个执行周期调度访问请求的总顺序队列（TOQ）。 访问请求被允许在需要时将共同资源分配给该请求来进行进展。 在多个访问请求需要相同的公共资源的情况下，优先级被赋予较旧的访问请求。 访问请求可能处于睡眠状态，等待某些公共资源的可用性。 可以通过允许较旧的访问请求从较年轻的资源请求中窃取资源来避免死锁。 所公开的技术的一个优点是较旧的公共资源访问请求不被重复阻止以通过较新的访问请求提前进展。

    RESOURCE MANAGEMENT SUBSYSTEM THAT MAINTAINS FAIRNESS AND ORDER
    5.
    发明申请
    RESOURCE MANAGEMENT SUBSYSTEM THAT MAINTAINS FAIRNESS AND ORDER 有权
    资源管理子系统维护公平和秩序

    公开(公告)号：US20130311999A1

    公开(公告)日：2013-11-21

    申请号：US13476791

    申请日：2012-05-21

    申请人： Michael FETTERMAN ,  Shirish Gadre ,  John H. Edmondson ,  Omkar Paranjape ,  Anjana Rajendran ,  Eric Lyell Hill ,  Rajeshwaran Selvanesan ,  Charles McCarver ,  Kevin Mitchell ,  Steven James Heinrich

    发明人： Michael FETTERMAN ,  Shirish Gadre ,  John H. Edmondson ,  Omkar Paranjape ,  Anjana Rajendran ,  Eric Lyell Hill ,  Rajeshwaran Selvanesan ,  Charles McCarver ,  Kevin Mitchell ,  Steven James Heinrich

    IPC分类号： G06F9/50

    CPC分类号： G06F9/5011 ,  G06F2209/507

    摘要： One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.

    摘要翻译： 本公开的一个实施例阐述了在与重放操作相关的公共资源访问请求的调度中维持公平性和顺序的有效方式。 具体地说，流式多处理器（SM）包括配置成通过一个或多个执行周期调度访问请求的总顺序队列（TOQ）。 访问请求被允许在需要时将共同资源分配给该请求来进行进展。 在多个访问请求需要相同的公共资源的情况下，优先级被赋予较旧的访问请求。 访问请求可能处于睡眠状态，等待某些公共资源的可用性。 可以通过允许较旧的访问请求从较年轻的资源请求中窃取资源来避免死锁。 所公开的技术的一个优点是较旧的公共资源访问请求不被重复阻止以通过较新的访问请求提前进展。

    Dynamic bank mode addressing for memory access
    9.
    发明授权
    Dynamic bank mode addressing for memory access 有权
    用于存储器访问的动态存储区模式寻址

    公开(公告)号：US09262174B2

    公开(公告)日：2016-02-16

    申请号：US13440945

    申请日：2012-04-05

    申请人： Michael Fetterman ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    发明人： Michael Fetterman ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/38

    CPC分类号： G06F9/3887 ,  G06F9/3851

    摘要： One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.

    摘要翻译： 一个实施例提出了一种用于基于银行模式将地址动态地映射到多存储体存储器的存储体的技术。 应用程序可以被配置为执行读取和写入访问每个存储体的不同位数的存储器，例如每个存储体32位，每个存储体64位或每个存储体128位。 在每个时钟周期上，可以从应用程序之一接收访问请求，并且基于所述存储体模式动态地映射访问请求的每个处理线程地址以产生一组存储体地址。 然后，银行地址用于访问多存储存储器。 允许不同的银行映射使每个应用程序避免存储器访问时的存储器冲突，与对所有访问使用单个存储库映射相比。

    DYNAMIC BANK MODE ADDRESSING FOR MEMORY ACCESS
    10.
    发明申请
    DYNAMIC BANK MODE ADDRESSING FOR MEMORY ACCESS 有权
    用于存储器访问的动态银行模式寻址

    公开(公告)号：US20130268715A1

    公开(公告)日：2013-10-10

    申请号：US13440945

    申请日：2012-04-05

    申请人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    发明人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    IPC分类号： G06F12/06

    CPC分类号： G06F9/3887 ,  G06F9/3851

    摘要： One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.

    摘要翻译： 一个实施例提出了一种用于基于银行模式将地址动态地映射到多存储体存储器的存储体的技术。 应用程序可以被配置为执行读取和写入访问每个存储体的不同位数的存储器，例如每个存储体32位，每个存储体64位或每个存储体128位。 在每个时钟周期上，可以从应用程序之一接收访问请求，并且基于所述存储体模式动态地映射访问请求的每个处理线程地址以产生一组存储体地址。 然后，银行地址用于访问多存储存储器。 允许不同的银行映射使每个应用程序避免存储器访问时的存储器冲突，与对所有访问使用单个存储库映射相比。