Differential fault analysis hardening apparatus and evaluation method
    1.
    发明授权
    Differential fault analysis hardening apparatus and evaluation method 失效
    差分故障分析硬化装置及评估方法

    公开(公告)号:US6108419A

    公开(公告)日:2000-08-22

    申请号:US013550

    申请日:1998-01-27

    IPC分类号: H04L9/06 H04L9/30 H04K1/00

    摘要: A method of evaluating a cryptosystem to determine whether the cryptosystem can withstand a fault analysis attack, the method includes the steps of providing a cryptosystem having an encrypting process to encrypt a plaintext into a ciphertext, introducing a fault into the encrypting process to generate a ciphertext with faults, and comparing the ciphertext with the ciphertext with faults in an attempt to recover a key of the cryptosystem.

    摘要翻译: 一种评估密码系统以确定密码系统是否能够承受故障分析攻击的方法,所述方法包括以下步骤:提供具有加密过程的加密过程以将明文加密成密文的步骤,将故障引入加密过程以生成密文 具有故障,并且将密文与具有故障的密文进行比较以尝试恢复密码系统的密钥。

    Apparatus and method for dynamic hardening of a digital circuit
    2.
    发明授权
    Apparatus and method for dynamic hardening of a digital circuit 失效
    数字电路动态硬化的装置和方法

    公开(公告)号:US5949248A

    公开(公告)日:1999-09-07

    申请号:US943021

    申请日:1997-10-02

    IPC分类号: H03K19/003 H03K17/16

    CPC分类号: H03K19/0033

    摘要: A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).

    摘要翻译: 单个事件不良(SEU)灵敏度控制系统(42)将数字电路(48)动态地硬化为单个事件的烦恼。 灵敏度控制系统(42)包括用于检测导致单个事件不正常的粒子(38)的量的镦粗率传感器(66)。 噪声容限控制电路(70)被配置为响应于颗粒量(38)来调节数字电路(48)的噪声容限(46)。 当颗粒密度(34)高时,噪声容限(46)增加,以将数字电路(48)的灵敏度降低到单个事件的不适。 此外,当粒子密度(36)低时,噪声容限(46)减小,以降低数字电路(48)的功耗水平。

    Secure virtual RAM
    3.
    发明申请
    Secure virtual RAM 审中-公开
    安全的虚拟内存

    公开(公告)号:US20080072070A1

    公开(公告)日:2008-03-20

    申请号:US11512561

    申请日:2006-08-29

    IPC分类号: G06F12/14

    CPC分类号: G06F21/10 G06F21/51

    摘要: A secure virtual RAM securely transfers data within a device having a secure, non-volatile memory and a host. The secure virtual RAM includes a memory management component configured to direct the transfer of the data between the non-volatile memory and a processor, and an encryption/decryption component coupled to the memory management component and configured to decrypt the data provided to the processor and encrypt the data provided to the non-volatile memory. The secure virtual RAM further includes an integrity check component coupled to the encryption/decryption component and configured to monitor functional integrity, a key storage component coupled to the encryption/decryption component and configured to receive cryptographic keys and provide the cryptographic keys to the encryption/decryption component.

    摘要翻译: 安全的虚拟RAM在具有安全,非易失性存储器和主机的设备内安全地传输数据。 安全虚拟RAM包括被配置为引导非易失性存储器和处理器之间的数据传送的存储器管理组件以及耦合到存储器管理组件的加密/解密组件,并被配置为对提供给处理器的数据进行解密, 加密提供给非易失性存储器的数据。 安全虚拟RAM还包括耦合到加密/解密组件并被配置为监视功能完整性的完整性检查组件,耦合到加密/解密组件并被配置为接收加密密钥并将加密密钥提供给加密/解密组件的密钥存储组件, 解密组件。