公开(公告)号：US20170329611A1

公开(公告)日：2017-11-16

申请号：US15592551

申请日：2017-05-11

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Sean Steedman ,  Brent Loertscher

IPC: G06F9/30 ,  G06F13/40 ,  G06F1/08

CPC classification number: G06F9/30149 ,  G06F1/08 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/30185 ,  G06F9/342 ,  G06F13/4018

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16 KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4 KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

公开(公告)号：US10255073B2

公开(公告)日：2019-04-09

申请号：US15592551

申请日：2017-05-11

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Sean Steedman ,  Brent Loertscher

IPC: G06F9/30 ,  G06F1/08 ,  G06F13/40 ,  G06F9/34

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.