公开(公告)号：US20240056332A1

公开(公告)日：2024-02-15

申请号：US18146865

申请日：2022-12-27

Applicant: Microchip Technology Incorporated

Inventor： William T. Baggett ,  Dixon Chen ,  Venkatraman Iyer

IPC: H04L12/40

CPC classification number: H04L12/40032

Abstract: Disclosed examples include a method. The method includes: conveying symbols from a PHY toward a MAC via a PHY-side of PHY-MAC interface; and filtering one or more symbols at an input of a PHY-side of an interface wrapper of the PHY-side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY-side of PHY-MAC interface; and a logic circuit provided at the PHY-side of PHY-MAC interface, the logic circuit comprising a symbol filter to filter one or more symbols conveyed via the PHY-side of PHY-MAC interface.

公开(公告)号：US20240031181A1

公开(公告)日：2024-01-25

申请号：US18479631

申请日：2023-10-02

Applicant: Microchip Technology Incorporated

Inventor： William T. Baggett ,  Venkatraman Iyer

IPC: H04L12/12 ,  G06F1/3209

CPC classification number: H04L12/12 ,  G06F1/3209

Abstract: An apparatus may include a physical layer device, a detection circuitry and a power control circuitry. the physical layer device provides one or more functions of a physical layer to interface with a shared physical transmission medium. The detection circuitry detects an indication of power control signaling on the shared physical transmission medium, and detects an indication of Ethernet signaling on the shared physical transmission medium. The indication of power control signaling is different than the indication of Ethernet signaling. The power control circuitry manages a power state of the apparatus at least partially responsive to an output of the detection circuitry.

公开(公告)号：US11775045B2

公开(公告)日：2023-10-03

申请号：US16781227

申请日：2020-02-04

Applicant: Microchip Technology Incorporated

Inventor： William T. Baggett ,  Venkatraman Iyer

IPC: G06F1/3234 ,  G06F13/20

CPC classification number: G06F1/3234 ,  G06F13/20 ,  G06F2213/40

Abstract: Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.