公开(公告)号：US12164773B2

公开(公告)日：2024-12-10

申请号：US17968049

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Capri ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.