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公开(公告)号:US12056464B2
公开(公告)日:2024-08-06
申请号:US17217861
申请日:2021-03-30
Applicant: Micron Technology, Inc.
IPC: G06F7/58
CPC classification number: G06F7/584
Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n−m bit LFSR with a range of 2n-m−1−k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n−m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n−m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.
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公开(公告)号:US20220317975A1
公开(公告)日:2022-10-06
申请号:US17217861
申请日:2021-03-30
Applicant: Micron Technology, Inc.
IPC: G06F7/58
Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n−m bit LFSR with a range of 2n−m−1−k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n−m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n−m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.
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