公开(公告)号：US20160307647A1

公开(公告)日：2016-10-20

申请号：US15156165

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： DONALD M. MORGAN ,  Sujeet Ayyapureddi

IPC: G11C29/00 ,  G11C17/16

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C29/78 ,  G11C29/787 ,  G11C29/88

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract translation: 公开了用于混合后包装修复的装置和方法。 一种这样的装置可以包括包括存储器单元和易失性存储器的封装。 易失性存储器可以被配置为存储对应于被认为是有缺陷的后封装的存储器单元的第一部分的有缺陷的地址数据。 该装置还可以包括解码器，其被配置为当与要访问的地址相对应的当前地址数据与存储在易失性存储器中的缺陷地址数据匹配时，选择存储器单元的第二部分而不是存储器单元的第一部分。 该装置还可以包括包装中的非易失性存储器。 该装置还可以包括封装中的映射逻辑电路。 映射逻辑电路可以被配置为在存储到易失性存储器的缺陷地址数据之后将替换地址数据编程到非易失性存储器。

公开(公告)号：US20180061483A1

公开(公告)日：2018-03-01

申请号：US15245067

申请日：2016-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DONALD M. MORGAN

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C7/04 ,  G11C11/40626 ,  G11C11/4076

Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.