公开(公告)号：US20220076726A1

公开(公告)日：2022-03-10

申请号：US17013402

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： David N. Hulton ,  Jeremy Chritz ,  Jonathan D. Harms

IPC: G11C11/406 ,  G06F11/07 ,  G06F16/2458 ,  G11C11/4096

Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.