公开(公告)号：US20240020018A1

公开(公告)日：2024-01-18

申请号：US17865203

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

公开(公告)号：US20240281151A1

公开(公告)日：2024-08-22

申请号：US18651032

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F3/06 ,  G11C7/04 ,  G11C11/406 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C11/40626 ,  G11C16/3418

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

公开(公告)号：US12001686B2

公开(公告)日：2024-06-04

申请号：US17865203

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F1/00 ,  G06F3/06 ,  G11C7/04 ,  G11C11/406 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C11/40626 ,  G11C16/3418

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.