公开(公告)号：US11573702B2

公开(公告)日：2023-02-07

申请号：US17331281

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

IPC: G06F1/12 ,  G06F1/04 ,  G06F3/06 ,  G06F11/10

Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

公开(公告)号：US11042301B2

公开(公告)日：2021-06-22

申请号：US16219218

申请日：2018-12-13

Applicant: Micron Technology, Inc.

Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

IPC: G06F1/12 ,  H04L5/00 ,  G06F3/06 ,  G06F11/10

Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.

公开(公告)号：US20210286516A1

公开(公告)日：2021-09-16

申请号：US17331281

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

IPC: G06F3/06 ,  G06F11/10

Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.