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公开(公告)号：US20250068520A1
公开(公告)日：2025-02-27
申请号：US18777453
申请日：2024-07-18
Applicant: Micron Technology, Inc.
Inventor： Antonino Caprì , John Namkung
IPC: G06F11/10
Abstract: A row can be mapped to a spare row in memory. The mapping can include stopping the scheduler from issuing commands to the first bank. Responsive to stopping the scheduler from issuing commands to the first bank, the logic can map a particular row of the first bank to the spare row. The mapping can include allowing the scheduler to schedule commands for the second bank concurrently with the mapping of the particular row to the spare row.
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