公开(公告)号：US20230305717A1

公开(公告)日：2023-09-28

申请号：US18125279

申请日：2023-03-23

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Luanming Deng

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a memory device including a memory array and control logic operatively coupled with the memory array. The memory array includes a target cell connected to a target wordline, a first cell connected to a first adjacent wordline adjacent to the target wordline, and a second cell connected to a second adjacent wordline adjacent to the target wordline. The control logic performs operations including causing a read to be performed with respect to the first cell to obtain an adjacent wordline read result, storing the adjacent wordline read result using a first set of page buffers, causing an incremental read to be performed with respect to the second cell and a first bin to obtain a first incremental read result, and storing the first incremental read result using a second set of page buffers.